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Page 1 of 1 (3 items)
  • The error of Synthesis
    Hi friends, I  synthesize a very simple veirlog code but I got an following error when I did "synthesize -to_mapped". There is nothing between the single quotes. How can I find what and where the error is? I will list my code and tcl file. BTW, I used RTL Compiler. Thanks. Error   : A required object parameter could not be ...
    Posted to Logic Design (Forum) by bravepanda on Tue, Sep 3 2013
  • Re: Question about the multiplier
    Hi Grasshopper, Thanks for your reply. I also have an question. If I use A=op1*op2, I cannot control the circuit and the timing. For example, if the verilog code is  always @(posedge clk or negedge rst) if (~rst) A <=0; else A<=op1*op2 ; In this code, I hope the multiplication can be finished in one clock cycle. If it ...
    Posted to Logic Design (Forum) by bravepanda on Tue, Sep 3 2013
  • Question about the multiplier
    Hello,   We are doing a design which needs the multiplier. Does Cadence RTL compiler has the library which is same as Synopsys Designware?   Thanks. 
    Posted to Logic Design (Forum) by bravepanda on Mon, Sep 2 2013
Page 1 of 1 (3 items)