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 Community Search 

Page 1 of 1 (10 items)
  • Re: Simulation problem: unwanted zero-width glitch
      Hi,You need to turn off "-event" switch when you are opening the shm waveform database. The default behavior is not to record these glitches (that you want), and it happens only when you specify "-event" option of 'database' tcl command. The following is copy-paste from NCVLOG product ...
    Posted to Functional Verification (Forum) by Amit Dua on Mon, Aug 24 2009
  • Tech Tip: Viewing The Combined Help for IES-XL
    IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode. One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very simple to achieve !!! So, I thought of sharing ...
    Posted to Functional Verification (Weblog) by Amit Dua on Fri, Feb 20 2009
  • Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator
    While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:Error! integer overflow File: ./test.vhd, line = 13, pos = 11 Scope: :$PROCESS_000 Time: 10 FS + 0 ./test.vhd:13 i := i - 1;Incisive is probably the only simulator to report such error ...
    Posted to Functional Verification (Weblog) by Amit Dua on Wed, Jan 28 2009
  • Re: long simulation time problem
      In the absence of specific details, the general performance suggestions are: - Look at the command line switches that can speed up the simulator. For example - -access, -linedebug switches should not be used for batch simulations. - Profile the simulation run (of about 10-15minutes). This can be done by simply adding "-profile" ...
    Posted to Functional Verification (Forum) by Amit Dua on Wed, Dec 17 2008
  • Re: error when passing a string to ncutils
      The argument of $nc_mirror can be string or a register. Now, when it is a string, it should be the hierarchical path of the object. When it is a register then it has to be the 'actual' register. Here you are trying to pass a register whose value is expected to be treated as a string. So, you need to either declare a string as ...
    Posted to Functional Verification (Forum) by Amit Dua on Wed, Dec 17 2008
  • Video Demo: “irun” – The Way to run Simulations!
    The irun utility provides a use-model to run simulations with Incisive Simulator in a simple and consistent manner.  The main benefit of irun is that it can simulate the multi-language design & verification environments in a single step by simply specifying all input source files and options on a single command line!! The following ...
    Posted to Functional Verification (Weblog) by Amit Dua on Wed, Dec 17 2008
  • Re: FSDB dump using IUS6.2-p1
      Novas fsdb dump can be generated with IUS simulator by plugging the Novas PLI with ncsim. The details are available in novas installation. However, IUS simulator supports a native format (SHM) that you may want to use & analyse in Simvision debug & analysis environment.  rgds, Amit.
    Posted to Functional Verification (Forum) by Amit Dua on Fri, Oct 24 2008
  • Re: How to Compile System Verilog
    Use irun to compile & simulate in a single step any/all hdl/hvl supported by Incisive platform. irun is a smart utility that can compile the file based on the default extension. Check the irun documentation in <ius_inst_dir>/doc/irun/irun.pdf  rgds, Amit
    Posted to Functional Verification (Forum) by Amit Dua on Fri, Oct 24 2008
  • Re: Directed vs Random Testing
      Hi Mike, Interesting topic. I agree with your thought that random & contraint random is an advanced & better way to do verification closure specially with metric driven verification based on coverage, but directed is not dead. However, I would like to add another aspect here. Verification is mostly done with both random and ...
    Posted to Functional Verification (Forum) by Amit Dua on Fri, Oct 24 2008
  • Re: How to mirror VHDL signal in verilog Top Test bench
    Venkat, The problem in your case is that the path specified in your nc_mirror is not correct. You need to get the correct path. The most likely cause seems to be that the vhdl top path starts with a ":" So instead of the top level entity/architecture, you replace it with ":" Moreover, there are a few easy ways to find out ...
    Posted to Functional Verification (Forum) by Amit Dua on Thu, Oct 23 2008
Page 1 of 1 (10 items)