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 Community Search 

Page 1 of 1 (4 items)
  • problem in getting power information from the given below verilog-AMS code
    i want to ask you is how to get power analysis data for verilog AMS code. i have tried with sample code given in cadence LRM but i have n't got any power information the code is given below  ‘include "disciplines.vams" module Res(p1, n1); inout p1, n1; electrical p1, n1; parameter real r=5; analog begin V(p1,n1) ...
    Posted to Custom IC Design (Forum) by sunilreddy on Sun, Sep 8 2013
  • Re: Have problem in simulating circuit in virtuoso ADE
    hai andrew it is verilog-AMS code and the error i got is same as  Problem while running verilog-ams block in cadence schematic editor started by indra http://www.cadence.com/Community/forums/p/26739/1325379.aspx#1325379 from that i got know that i need to setup AMS environment. i studied the user manual but i am unable to get it as i ...
    Posted to Custom IC Design (Forum) by sunilreddy on Fri, Aug 16 2013
  • can we attach technology file to verilog-AMS design
    Hai all  I am new to cadence and verilog-AMS i am trying to design ADC circuit completely in verilog-AMS description. i have a doubt that whether we can attach technology file(65nm or 180nm) to this design codes and get the power consumption of the circuit .if any one says yes we can then tell me how to attach the technology file and get ...
    Posted to Mixed-Signal Design (Forum) by sunilreddy on Fri, Aug 16 2013
  • Have problem in simulating circuit in virtuoso ADE
    Hi  I generated a ideal adc from model writer option and then i created symbole for that.  I created a test bench for that model but when i simulate using virtuoso ADE i am getting error The error is in my verilog module i defined as a register dout<7:0> but when i created the netlist from the schematic it is taking individual ...
    Posted to Custom IC Design (Forum) by sunilreddy on Sat, Jul 27 2013
Page 1 of 1 (4 items)