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 Community Search 

Page 1 of 2 (14 items) 1 | 2 | Next >
  • Re: Assura extraction to ignore certain cells
     I looked up the log file  and here is what I see ...   *WARNING* Binding file Conflict!     ExpandToParent is requesting to expand Binding cell "RCCAL_INT layout CAL".     Expansion will be allowed.  Be aware that this expansion may cause LVS matching problems.   *WARNING* ...
    Posted to Custom IC Design (Forum) by kawan on Mon, Apr 7 2014
  • Re: Assura extraction to ignore certain cells
     Yes, I think the pronlem is in the LVS. In the hierarchy editor, that particular cell does not show up. I open the layout view "extracted view" and I see that it has been extracted.That one cell cannot be switched to a schematic or any other view. I did not save the log file , else I can post it here. If I get back to that I will ...
    Posted to Custom IC Design (Forum) by kawan on Mon, Apr 7 2014
  • Re: Assura extraction to ignore certain cells
     Quek, Thanks!, That was excatly what I ended up doing after a Cadence rep gave me the same directions. I did not post a reply back on thsi as I was still having some issues. The method worked for all but one cell in the hierarchy ... I just cannot explain it. But overall, it did what I wanted it to do.   Thanks zakir
    Posted to Custom IC Design (Forum) by kawan on Mon, Apr 7 2014
  • Assura extraction to ignore certain cells
     Hello, I am trying to run an extraction of  a top level cell(say "test_top"). Hoever there is another cell inside ("Cell1") that I do not wish to extract.My expectation is I get get a extracted view called "av_extracted_C" which I can refer to in the hierarchy editor of the top level testbench ...
    Posted to Custom IC Design (Forum) by kawan on Mon, Mar 24 2014
  • printing voltages and currents after transient or dc operating point simulations
    Is there a way for me to run a simulation and have it write out a text file stating the voltages and currents of all nodes saved? The simulation would be a dc operating point or a transient where I specifiy the time for printing. It is exactly like annotating the operating point. I can do this in the ADE window, but do not want to see it ...
    Posted to Mixed-Signal Design (Forum) by kawan on Thu, Nov 14 2013
  • Re: how to pass array of parameters through CDF down to a verilogA code?
     Andrew, I ran into the same problem and I tried out your solution. It did not work and I wonder if the solution is now different with cadence 6.1.5 ?  // VerilogA for zakir_sim1, bb_prereg_ldo, veriloga `include "constants.vams" `include "disciplines.vams" module trim3bits(sel); output [2:0] sel; electrical ...
    Posted to Custom IC Design (Forum) by kawan on Tue, Oct 8 2013
  • Re: saving ams config hierarchy
     Thanks. I will try this out.   zakir
    Posted to Mixed-Signal Design (Forum) by kawan on Fri, Aug 30 2013
  • saving ams config hierarchy
    let us say I have a testbench running ams. There is a cell in there called pll_top. It is very complex  and deep. As such I have a particular set of views instantiated all the way in the tree. Once this works, I now instantiate the whole chip in another testbench. There are now other cells involved but pll_top is still there. Is there not a ...
    Posted to Mixed-Signal Design (Forum) by kawan on Fri, Aug 16 2013
  • Re: modifying pin names of a symbol
     Yes , That does do what I want in an easy way. I have it going that way now. Thank You! zakir
    Posted to Custom IC SKILL (Forum) by kawan on Tue, Aug 13 2013
  • Re: modifying pin names of a symbol
     Andrew, On another note ... it is a different issue , I can start a new thread if you think so .. I will take an empty schematic and instantiate a block that has a few hundred pins on it. But I now want to automatically wire each pin  of that block to another pin that has the same identical name. The only reason I am doing this is ...
    Posted to Custom IC SKILL (Forum) by kawan on Fri, Aug 9 2013
Page 1 of 2 (14 items) 1 | 2 | Next >