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  • Re: RTL compiler to minimize area
    Hey Guys, Thank you for your help. gh, when I do multiple mapping, the synthesis result is different I don't know why. sometimes, the area geos form 630 to 570. and sometime if you make more mapping the area goes up again. !! I used to run DC before I switch to RC. DC has a better performance in terms of Area optimization. I guess ...
    Posted to Logic Design (Forum) by Hamzah on Wed, Jun 19 2013
  • RTL compiler to minimize area
    Hello all,   I am using RTL compiler to synthesize a pure combiniational digital designs. I would like to know how to constraints the synthesis tool to minimize the Area as its first periority or even may be the only periority.   The shell script I use to synthesis my designs is:#/bin/sh SYN_ID=$2 FILE=$1 SYN_TOOL=rc ...
    Posted to Logic Design (Forum) by Hamzah on Fri, Jun 14 2013
Page 1 of 1 (2 items)