Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (8 items)
  • Re: deepprobe with AMS
     That's a shame..... ok...I'll continue to use 'force' 'release' statements to 'logic' discipline nets for now.  Cheers
    Posted to Custom IC Design (Forum) by KMan11 on Fri, Jul 19 2013
  • Re: deepprobe with AMS
     Hi Guys,  Did anyone try the deep probe (with or without the additional SKILL) with an OSS netlister?   I did manage to get it to work with Cell-view, but I recently changed over to OSS to support up-to-date features.   Whilst the simulation runs with the deepprobe, I get a warning during a transient run preamble, that ...
    Posted to Custom IC Design (Forum) by KMan11 on Fri, Jul 19 2013
  • Re: Dynamic parameter and verilogA code
     Hi Andrew.   Our Cad guy downloaded, built and installed Spectre 12.1.1 32 bit sub version : 12.1.1.059.isr10   Attached is an image of shownig fast clocking and then slow clocking of the data from file   Thanks for your help    
    Posted to Custom IC Design (Forum) by KMan11 on Fri, Jul 12 2013
  • Re: Dynamic parameter and verilogA code
     Hi Andrew, Thanks for going to the effort to itierate out the problem.  Can see the option to attach an image in the reply box, so I cut and pasted it...perhaps it was moderate. I'll ask if we can upgrade our MMSIM  All the best   KMan11
    Posted to Custom IC Design (Forum) by KMan11 on Tue, Jul 9 2013
  • Re: Dynamic parameter and verilogA code
    Hi Andrew,  You'll see above, the image from my simvision of your code.  I run the following command from UNIX :  spectre test.scs +escchars +log ./psf/spectre.out -format sst2 -raw ./psf test.scs contains the instantiations and analysis info Rest is as you have it  I've attached a log of the run below (sorry ...
    Posted to Custom IC Design (Forum) by KMan11 on Mon, Jul 8 2013
  • Re: Dynamic parameter and verilogA code
     Hi Andrew, So I bundled your code into 2 files : test.scs containing the instantiation and dynparam.va as you have it and simulated at the UNIX command line as follows :  spectre test.scs +escchars +log ./psf/spectre.out -format sst2 -raw ./psf and in simvision, I open the .trn file and I get the waveform at the bottom of the ...
    Posted to Custom IC Design (Forum) by KMan11 on Mon, Jul 8 2013
  • Dynamic parameter and verilogA code
    Hello   I have a VerilogA block which reads in single binary bits from a file, on rising edges of an incoming clock (generated by VPULSE).  I created a simple file where I have tscale and tscale_value and time and period values. The 'period' parameter, incidentally, changes the period of the incoming clock.  I ...
    Posted to Custom IC Design (Forum) by KMan11 on Thu, Jul 4 2013
  • properties unresolved during OSSHNL-366
    Hi,  I'm battling AMS netlisting issues in IC6.1.5. I'm trying to use an OSS netlister to netlist and run an database.  I had it working, yet when I created another config view with the same 'view' of a block of IP, I get the following error .......... ERROR (OSSHNL-366): instance * in cellview ...
    Posted to Custom IC Design (Forum) by KMan11 on Tue, Jun 11 2013
Page 1 of 1 (8 items)