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  • Re: power differences after post-syn using VCD
    Hey, gh  Thanks for your reply. What I want to compare is netlist(after syn) + gate_VCD(without sdf annotation) VS netlist(after syn) + gate_VCD(with sdf annotation). The power analysis tool is ETS for both. The sdf is generated after syn. The netlist is the same. In your reply you said you noticed the annotation is different yet I used ...
    Posted to Logic Design (Forum) by leez2006 on Thu, Jul 25 2013
  • power differences after post-syn using VCD
    Hi, I want to get a quick look at the power consumption of one block. --use RTL Compiler generate netlist(after syn) and sdf --run gate sim with or without sdf annotated, get VCD --use netlist and VCD in ETS, get power consumption I found the power consumption get form VCD without sdf annotated is much greater than with sdf ...
    Posted to Logic Design (Forum) by leez2006 on Wed, Jul 24 2013
Page 1 of 1 (2 items)