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  • Re: Verilog simulation using verilog XL
    Hi ,           I am getting the error while simulating the Verilog  in cadence which is integrated with an inverter block made from nmos_hvt and pmos_hvt of PDK library. verilog is a symbol generated in cadence from the verilog file.  Error!    Module or primitive (verilog) not ...
    Posted to Logic Design (Forum) by PranR on Sun, Apr 21 2013
Page 1 of 1 (1 items)