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 Community Search 

Page 1 of 2 (14 items) 1 | 2 | Next >
  • IO filler cell violations power routing
    Hello, I am trying to do the power routing of the IO pads in my design. I connected all the power and ground pins using global net connect command.   globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {}  globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {}  globalNetConnect vdd -type pgpin -pin {VDD} ...
    Posted to Digital Implementation (Forum) by amythpai on Tue, May 14 2013
  • Routing of Power Pins of IO pad Pins
    Hello, I want to route the power pins of IO pads like the vdd, gnd, A0SRC and all. I have run the global net connect command : globalNetConnect VDD -type pgpin -pin {vdd} -inst * -module {}  globalNetConnect GND -type pgpin -pin {gnd} -inst * -module {} I then tried to route using sroute to route the pins but the metal layer used is ...
    Posted to Digital Implementation (Forum) by amythpai on Mon, May 6 2013
  • Minstep violation and Minhole violation
    Hello. I am geting error like Minstep violations while doing place and route in the layouts of my full custom designs. Also there  some Min hole violations in standard cells IO pads. Can any one please tell me how these violations can be corrected or avoided? 
    Posted to Digital Implementation (Forum) by amythpai on Sun, Apr 28 2013
  • CTS and Routing
    Hello. I have some doubts regarding clock tree generation and routing. I am just a beginner in this field, so certain question might seem trivial: 1. Is the CTS done before the routing process or after the routing process. 2. I was trying the optimisation option in SOC encounter before routing and it inserts buffers for the two clocks which I ...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Apr 28 2013
  • Re: Specify the metal Layers in SOC encounter
    Hello... I tried it yesterday.. But there seems to be no change in the number of errors!!
    Posted to Digital Implementation (Forum) by amythpai on Thu, Apr 4 2013
  • Re: Specify the metal Layers in SOC encounter
    hello... Sorry for the delay. I wasnt in town. Actually I think I know what the problem might be. It may just be the case of wrong units or grids . I was just comparing the two i.e the SOC encounter and the layout from virtuoso and I found that the two have a difference in spacing. For example in the SOC encounter the two metal 1 layers have ...
    Posted to Digital Implementation (Forum) by amythpai on Tue, Apr 2 2013
  • Re: Specify the metal Layers in SOC encounter
    DRC tool used : CalibreProcess: Cmos065 We have certains cells which are custom defined at the layout level and we have written the LEF file on our own, I think this may be the route cause of the problem! In the Lef file we have individually described all the metal pins and theobstructions, but the routing produces DRC errors( valid errors) which ...
    Posted to Digital Implementation (Forum) by amythpai on Wed, Mar 27 2013
  • Re: Specify the metal Layers in SOC encounter
    Thank you for your Quick reply. Actually I have tried this but it resulted in a lot of DRC violations. My probelm is that I had initially routed using default option for routing layers. I ran the verify geometry command and it didnot result in any violations. But when I exported the gds file in to virtuoso and ran the DRC check it resulted in ...
    Posted to Digital Implementation (Forum) by amythpai on Wed, Mar 27 2013
  • Specify the metal Layers in SOC encounter
    Hello,  I am a newbie at placement and routing. I want the routing to be done using only metal 3,4 and 5 ( basically other than metal 1 and 2). Can anyone please advise me as to where I have to mention this and the command used to get routing metal layers set?    Any help in this regard is appreciated! Thank you 
    Posted to Digital Implementation (Forum) by amythpai on Tue, Mar 26 2013
Page 1 of 2 (14 items) 1 | 2 | Next >