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 Community Search 

Page 1 of 1 (1 items)
  • synthesis warning of undriven signal
     If there are some undriven signals in my design,can RTL-Compiler find that?  Is there any synthesis "warning", "Info" or "Error about this issue? Should I set any attribure to find this problem?     Here are some sample code: module mydesign (A, B) ; input [3:0] A; output [3:0] B; wire ...
    Posted to Logic Design (Forum) by projectd2007 on Tue, Mar 12 2013
Page 1 of 1 (1 items)