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# Community Search

Page 1 of 1 (8 items)
• Re: Intrinsic capacitance Cbs
Dear Shawn, Thank you very much for your quick reply.I believe I understand your answer, but let me make sure of this.Summarizing your aforementioned thoughts, the nonzero Cbs lies on the fact that the parasitics between source and bulk contacts (arising from layout) may contribute to some displacement current. Thus, a nonzero Vsb may arise ...
Posted to Custom IC Design (Forum) by ronaldomponte on Wed, May 14 2014
• Intrinsic capacitance Cbs
I am simulating a conventional ring oscilator with pmos and nmos devices comprising the inverter cell. Bulk and source terminals are shorted, so Vsb = 0.  As the intrinsic capacitive coefficients are defined as Cij = dQj/dVj in Bsim3v3 model, it should be predicted that the Cbs = 0 (since Vs=0). However, inspecting the nfet and pfet DC ...
Posted to Custom IC Design (Forum) by ronaldomponte on Wed, May 14 2014
• How to recover an unsaved parametric simulation in ADE-L
============================================================================= Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 12.1.0.272 32bit -- 25 Sep 2012 virtuoso -W: sub-version  IC6.1.5.500.7  spectre -W:   /usr/EDATools/cadence/mmsim121/tools.lnx86/spectre/bin/32bit/spectre: ...
Posted to Custom IC Design (Forum) by ronaldomponte on Mon, Mar 17 2014
• Re: Problems to run PSP and BSIM3 compact models in verilog-A
Wow Andrew,  Very very helpful solution! It fixed both cases. Thank you very much. As a stated before, I'm a new user in cadence tools. So, that was the way I found to test the models and probably is not the best one. Could you explain or give me directions on how can I use/select the built-in models in spectre? Or maybe I need to add ...
Posted to Custom IC Design (Forum) by ronaldomponte on Wed, Nov 6 2013
• Problems to run PSP and BSIM3 compact models in verilog-A
============================================================================= Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 12.1.0.272 32bit -- 25 Sep 2012 virtuoso -W: sub-version  IC6.1.5.500.7  spectre -W:   /usr/EDATools/cadence/mmsim121/tools.lnx86/spectre/bin/32bit/spectre: ...
Posted to Custom IC Design (Forum) by ronaldomponte on Tue, Nov 5 2013
• ISFET layout design
Hello, Is it possible to design an ISFET sensor thru Cadence Design Enviroment tools?  If it is possible, I guess it may be necessary to breach some design rules, isn't it? Could anyone guide me thru this specific design? How can I breach the design rules? Is it possible to coat different materials (e.g. Si3N4) over the gate insulator? ...
Posted to Custom IC Design (Forum) by ronaldomponte on Mon, Sep 16 2013
• Help adding model parameters in Object Properties of a component
Hello,  I am using Virtuoso Analog Design Enviroment in order to perform some simulations in Spectre with an nmos cell from the AnalogLib. The issue is that I would like to add some model parameters of the nfet.scs file (e.g. tox, vth0_n, u0 etc.) in the CDF parameters of the nmos cell. Thus I can set those model parameters as ...
Posted to Custom IC Design (Forum) by ronaldomponte on Mon, May 20 2013
• Parametric analysis in AMS simulator
Hello, I am trying to run a DC parametric analysis using the AMS simulator, but it does not give me any results. I have realized that the 'DC analysis' in AMS simulator is only possible saving the DC operating point, which does not give me the chance to run a parametric analysis (once it does not save me any parameter value). I still ...
Posted to Custom IC Design (Forum) by ronaldomponte on Mon, Mar 11 2013
Page 1 of 1 (8 items)