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 Community Search 

Page 1 of 1 (4 items)
  • Martin Lund on the Future of IP (Video Interview)
    As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.Martin Lund, Senior Vice President at Cadence, was recently interviewed at ...
    Posted to Design IP and Verification IP (Weblog) by Neil Hand on Wed, Jun 13 2012
  • New Memory Technologies, New Possibilities
    As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will ...
    Posted to Design IP and Verification IP (Weblog) by Neil Hand on Mon, Apr 11 2011
  • Effectively communicating Low-Power and Power-Efficient Design knowledge
    For those of you interested in the Power space I recently had an article published on the Power Management DesignLine Europe website that talks about the challenges of capturing and communicating expertise and best practices throughout an organization (both large and small). The article talks about the ideas behind creating a design kit focused ...
    Posted to Digital Implementation (Weblog) by Neil Hand on Wed, Sep 3 2008
  • Customer Experiences With Low-Power Design
    Hello and welcome to the new Cadence community site, and my first blog post. You will see me here from time to time posting on topics and trends in the Power Efficient Design and Low Power Design area -- and most importantly, how we as a community can play a bigger part in ensuring your success.   If you have any topics you would like to ...
    Posted to Digital Implementation (Weblog) by Neil Hand on Sun, Jul 13 2008
Page 1 of 1 (4 items)