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 Community Search 

Page 1 of 1 (6 items)
  • Clock Netlist export and import to Cadence Virtuoso
    Hi everyone! Does anyone had succeed in importing SPICE Netlist into Cadence Virtuoso? I have tried several times but it seems something is wrong and I can not really get it work. The thing which I am dealing with right now is like this. 1.A design was fully place and route in Cadence Encounter 2.I was succeed in extracting the SPICE Netlist ...
    Posted to Custom IC Design (Forum) by Yuqi on Fri, Apr 26 2013
  • Unbuffered Clock Tree
    Hello everyone,  Does anyone knows how to constraint Encounter to construct Unbuffered Clock Tree? The reason that I am interested in the unbuffered one is because that I am focusing on the sub-vt CTS construction and I have read some papers refer to the unbuffered clock tree.   Thanks in advance! Yuqi
    Posted to Digital Implementation (Forum) by Yuqi on Thu, Apr 18 2013
  • Placing certain group of instance
    Hi everyone,  Wondering if it is possible to place certain group of instance at the beginning of the PNR flow? Not a single of. Because I know that placeInst  could be used for placing single instance. But the thing is that I have a bunch of these instance to be placed and I cannot do it manually.   Thanks for any ...
    Posted to Digital Implementation (Forum) by Yuqi on Thu, Mar 28 2013
  • Re: clock tree synthesis for clock gating
    Did you try the throughPin option in the clock specification file? Maybe it works. BR Yuqi 
    Posted to Digital Implementation (Forum) by Yuqi on Wed, Feb 27 2013
  • Level of the Clock Tree
    Hi everyone, I wonder if it is possible to specify the level of clock tree to be synthesized in socecounter? I mean tell the tool that I want 3 level tree and that it finds that most suitable? I noticed that there is a option named maxNumLevel in autoCTS specification file. But this command can only specify the maximum allowable level instead of ...
    Posted to Digital Implementation (Forum) by Yuqi on Mon, Feb 25 2013
  • Manual CTS report
    Hi everyone, I am currently doing a project mainly focus on clock tree synthesis in Cadence Soc Encounter. As I need  to study different topology of clock trees, I am using the manual mode CTS. What I have done is: 1.use specifyClockTree command to read in the ctstch file 2.use ckSynthesis command to do the actual clock tree ...
    Posted to Digital Implementation (Forum) by Yuqi on Wed, Feb 6 2013
Page 1 of 1 (6 items)