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 Community Search 

Page 1 of 23 (227 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: Processing cadence result data from psf folder
     Hi Swann, When I typed  outputs, it shows:-  ("V2_OUTP_Q:p") But NOT as   ("/V2_OUTP_Q/PLUS"). I am NOT able to understand why it is NOT showing  ("/V2_OUTP_Q/PLUS") as when I run with ocean script.  
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jul 11 2014
  • Re: Processing cadence result data from psf folder
     I used the same commands used in my ocean scripts as below:-  openResults("psf") selectResult( 'tran ) plot(getData("/V2_OUTP_Q/PLUS")) But it didn't work. But when I run the simulation, using OCEAN script ( i.e. load(".../../xxxx.ocn) ) it plots . I am not able to understand why  ...
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jul 11 2014
  • Processing cadence result data from psf folder
     Dear All,  There is a Spectre & MATLAB interface for plotting psf data. But this somehow not working in my case with latest MATALB2014. So I use Ocean Script for saving simulation data in text file in two column format. This then being used some other plotting tools like MATLAB. But when we run Spectre in our central server, we ...
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jul 11 2014
  • Re: Importing .gds file in virtuoso
    Yes Andrew, That indeed worked. Kind Regards,  
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jul 11 2014
  • Importing .gds file in virtuoso
    Dear All, I have got a .gds file from a foundry person. Basically, it has some ERC errors locations markers in the layout in it. When I tried it to stream in, I found the follwing errors.  FATAL (299): Stream In is unable to find the structure definition for the primary cell in the stream file. Ensure that you have specified the correct ...
    Posted to Custom IC Design (Forum) by RFStuff on Wed, Jul 9 2014
  • Assura LVS errors
     Dear All,  We are switchig to ASSURA (sub-version 4.1_USR4_HF3) from CALIBR. But we are seeing following errors in LVS log file. These errors were NOT shown by CALIBRE. 1:- Executing: nnbdif = geomButtOnly(nsd ptap diffNet) errorLayer(nnbdif " nsd/ptap butting issue: nsd/ptap need to be connected by metal and ...
    Posted to Custom IC Design (Forum) by RFStuff on Sat, Jul 5 2014
  • Generating ocean script in Linux terminal.
     Dear All, I am currently creating oceanScript.ocn by Session -> Save Ocean Script in ADE (in IC5141). But I want to generate the same from a Shell Script. Is there any way to generate from bash terminal ? or any SKILL script that will do the above which is going to be invoked by SHELL script. Kind Regards,
    Posted to Custom IC Design (Forum) by RFStuff on Mon, Jun 30 2014
  • Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)
    Dear All, I am facing issues with Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151) in my machine. My layout is having a lot of transistors ( like SRAM or DAC) in a small area. While doing zooming-in or zooming-out of the layout ( i.e. EDIT in place EIP ) of the cell, it becomes slow ( 2 to 3 seconds) for the layout-window to ...
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jun 27 2014
  • Labels are created in VLE while doing streaming in a GDS file.
     Dear All, I streamed in  a GDS file into a new library. While opening the top-level cell of the  library in the layout editor (VLE) , I find a lot of text labels ( like I1,I2...I1667) are created in the editor.  What I should do so that these labels will not be created automatically. I am using  IC5141-sub-version ...
    Posted to Custom IC Design (Forum) by RFStuff on Fri, Jun 27 2014
  • Re: very long bit pattern for vbit source
     Dear Andrew, I have a file data in column fromat. That is, instead of  [ p1 pattern data="10111011011" ], I have in the file ( named clk_bit.txt ) as below:- 1 0 1 1 1 0 1 . . . 1 0   Is it possible to source this file in the VSOURCE, without editing the above file. If so, could you please tell how it ...
    Posted to Custom IC Design (Forum) by RFStuff on Mon, Jun 16 2014
Page 1 of 23 (227 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »