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 Community Search 

Page 1 of 6 (51 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Changing the legened postion by default in viva
    Is there any way to change the legend position in viva so that it shows above the plot always? Every time, I plot a simulation, I have to go to graph, properties, and graph options to change the legend position from left to above. Thanks in advance.
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Obtaining zero temperature coefficient
     I am also including my net list: // Generated for: spectre // Generated on: Aug  6 07:51:55 2013 // Design library name: Baker // Design cell name: Ex23pa // Design view name: schematic simulator lang=spectre global 0 parameters Ln=250n Wn=1000n _gpar0=0 include "design.scs" include "allModels.scs" section=tt // ...
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Obtaining zero temperature coefficient
     Hello Andrew and Marc:  What I had originally is exactly as Andrew put it. I swept my VGS from 0.1 – 1.2V and did parametric sweep for temperature – 0:25:100. But I do not get the zero crossing point. I get the same curves at different temperatures. I am using psp model in IBM8HP 130nm process and I have selected tt for ...
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Design Variable and Global Variable.
     Andrew: When I do RMB (right mouse button), over at the Design Variable in the Data view assistant in ADE XL,  update option wont show up.  Thanks
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Obtaining zero temperature coefficient
    I am trying to simulate to obtain a zero temperature coefficient of an NMOS. I swept gate-source voltages and probed the drain current and did step temperature in parametric analysis and for some reason, I do not get the temperature displayed at different values. I am attaching the image of what I am trying to do.    Thank you ...
    Posted to Custom IC Design (Forum) by wgtkan on Mon, Aug 5 2013
  • Design Variable and Global Variable.
    When I create a Design Variable, it automatically get copied into Global variable. Whenever I change my design variable value, it doesn’t get updated in the global variable. I am using Virtuoso Analog design environment Version 8c6.1.5-64b.500.15. This happens in Virtuoso Analog Design environment XL. Thank you.  
    Posted to Custom IC Design (Forum) by wgtkan on Mon, Aug 5 2013
  • Re: Error when creating newlibrary
     When I typecdswhichsetup.loc I get a response that says nil
    Posted to Custom IC SKILL (Forum) by wgtkan on Mon, Jun 10 2013
  • HSPICE Error
    I am getting an error : Error nvSetVal: Can't set the value of variable 'includeSyntax',             in tool[.partition] 'hspiceD.envOpts' - it has not been registered. It has to do with hspiceD.envOpts  includeSyntax    string  "hspice" ...
    Posted to Custom IC Design (Forum) by wgtkan on Wed, Jun 5 2013
  • Error when creating newlibrary
    Unable to create library “Name” dd CreateLib: newly created library not found using normal search rules perhaps “.” Isn’t the first entry ‘in force’ setup.loc file(?) Every time I try to create a new library under IBM PDK menus  --à library àcreate -à in New Library window I put ...
    Posted to Custom IC SKILL (Forum) by wgtkan on Wed, Jun 5 2013
  • How to add section in my .cdsenv
    I would like to select a default option for corner options to tt (typical typical) and to make my model files simpler and easier to understand I have written the following in my .cdsenv: spectre.envOpts    modelFiles   string  "design.scs allModels.scs" spectre.envOpts    includePath  ...
    Posted to Custom IC SKILL (Forum) by wgtkan on Wed, Jun 5 2013
Page 1 of 6 (51 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »