Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 6 (54 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Obtaining Rds from the transistor
    Hello: I have a quick question. What is the Rds (the drain-source) output resistance called in the dc result browser? I see Ron, Rdeff, Rseff, Rgdb? Which one is it? Is it possible to obtain it from the transistor and during a dc sweep analysis? I was going to save it and plot is vs Vds. Thank you
    Posted to Custom IC SKILL (Forum) by wgtkan on Thu, Jun 12 2014
  • Re: Plotting Gm vs Vgs for different values of Vbs
    Dear Andrew:  I created an include file using a text editor in my case (gedit) and saved is as save.scs which contains save T1:gm the name of my transistor is T1.  I included this in ADE via Setup-> Model Libraries. First I did a dc sweep of Vgs from 0 to 1.5 in a linear step Mode of total 100 points. Then I did and a parametric ...
    Posted to Custom IC Design (Forum) by wgtkan on Wed, Jun 11 2014
  • Plotting Gm vs Vgs for different values of Vbs
    I would like to plot Gm vs. Vgs for different value of Vbs. Here is what I did. I performed DC sweep on Vgs and then plotted the drain current vs Vgs and then carried out derivative of ID with respect to VGS using the calculator, i.e derv(IS(drain)) to obtain GM. Then performed a parametric analysis of different values of Vbs. Then when I did ...
    Posted to Custom IC Design (Forum) by wgtkan on Wed, Jun 11 2014
  • Changing the legened postion by default in viva
    Is there any way to change the legend position in viva so that it shows above the plot always? Every time, I plot a simulation, I have to go to graph, properties, and graph options to change the legend position from left to above. Thanks in advance.
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Obtaining zero temperature coefficient
     I am also including my net list: // Generated for: spectre // Generated on: Aug  6 07:51:55 2013 // Design library name: Baker // Design cell name: Ex23pa // Design view name: schematic simulator lang=spectre global 0 parameters Ln=250n Wn=1000n _gpar0=0 include "design.scs" include "allModels.scs" section=tt // ...
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Obtaining zero temperature coefficient
     Hello Andrew and Marc:  What I had originally is exactly as Andrew put it. I swept my VGS from 0.1 – 1.2V and did parametric sweep for temperature – 0:25:100. But I do not get the zero crossing point. I get the same curves at different temperatures. I am using psp model in IBM8HP 130nm process and I have selected tt for ...
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Re: Design Variable and Global Variable.
     Andrew: When I do RMB (right mouse button), over at the Design Variable in the Data view assistant in ADE XL,  update option wont show up.  Thanks
    Posted to Custom IC Design (Forum) by wgtkan on Tue, Aug 6 2013
  • Obtaining zero temperature coefficient
    I am trying to simulate to obtain a zero temperature coefficient of an NMOS. I swept gate-source voltages and probed the drain current and did step temperature in parametric analysis and for some reason, I do not get the temperature displayed at different values. I am attaching the image of what I am trying to do.    Thank you ...
    Posted to Custom IC Design (Forum) by wgtkan on Mon, Aug 5 2013
  • Design Variable and Global Variable.
    When I create a Design Variable, it automatically get copied into Global variable. Whenever I change my design variable value, it doesn’t get updated in the global variable. I am using Virtuoso Analog design environment Version 8c6.1.5-64b.500.15. This happens in Virtuoso Analog Design environment XL. Thank you.  
    Posted to Custom IC Design (Forum) by wgtkan on Mon, Aug 5 2013
  • Re: Error when creating newlibrary
     When I typecdswhichsetup.loc I get a response that says nil
    Posted to Custom IC SKILL (Forum) by wgtkan on Mon, Jun 10 2013
Page 1 of 6 (54 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »