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Page 1 of 1 (2 items)
  • Failure of liveness property
    Hi everybody I'm trying to verify the following property:-- psl assert_p1: assert always ( (CS = st_idle) -> next eventually! ((CS = st_get_ack) or (CS = st_set_ack)) ); The section "Waveforms for Liveness Assertions" of chapter 9 on the document Formal Verifier User Guide says: "A failed liveness assertion has an associated ...
    Posted to Functional Verification (Forum) by Wesh on Wed, Feb 20 2013
  • Verification of concurrent modules with IFV
    Hi guys, This is my first post. So, I hope I'm writting it in the correct place.  I need a help to verify two concurrent modules (A and B) instantiated in a top module (Top). The concurrent modules implements a state machine and I want to verify if a given signal is 1,  the module A is on state x and B is on state y. Is ...
    Posted to Functional Verification (Forum) by Wesh on Wed, Jan 9 2013
Page 1 of 1 (2 items)