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 Community Search 

Page 1 of 1 (4 items)
  • Re: Need help in assertion based connectivity checking (solved)
    Hi, Got this doubt cleared. The sarch command will never show a pass result it will always show explored for the assertions that are passing. This is because search command runs a simulation .It will not run exhausively. We need to issue prove command to thorougly verify the design. Thanks a lot for help. Regards, Snehal
    Posted to Functional Verification (Forum) by SnehalC on Tue, Jan 22 2013
  • Re: Need help in assertion based connectivity checking
    Hi Joerg, Thanks a lot for the help you provided. I could find out coverage now. It is good to hear that covers are being added to connectivity checks. While I was trying some more options in IFV, I found the option for the debug solver waveform. I added searchpoints and ran the search command for 5 cranks. The debug -solver command gave ...
    Posted to Functional Verification (Forum) by SnehalC on Mon, Jan 7 2013
  • Re: Need help in assertion based connectivity checking
    Hi Joerg, When I ran the same script with PSL, clock was not generated. I previously though that it was due to the HDL language (VHDL/Verilog). I had one more question: How do we enable the builtin toggle coverage? I was not able to find any such option in the tool. Your information was really useful for me. Thanks a lot. Regards, Snehal
    Posted to Functional Verification (Forum) by SnehalC on Wed, Jan 2 2013
  • Need help in assertion based connectivity checking
    Hi, I am new to the formal verification process and I am trying to use it for verifying the connectivity between some modules in a SoC. I am using Incisive Formal SoC Connectivity Solution (V2.01) speadsheet to create the property file for the specified connections. While verifying the connections I am finding certian issues: 1. The ...
    Posted to Functional Verification (Forum) by SnehalC on Sun, Dec 30 2012
Page 1 of 1 (4 items)