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  • Re: Query in Naming in schematic and layout
    Hi Andrew Sorry for the lesser details. I am using spectre.I have a problem to use global power and ground in Cadence6. I use vdd! and vss! in my schematics. They are recognized in different hierarchy in schematic simulation, so no problem. However, they are a problem when I would like to run a testbench ...
    Posted to Custom IC Design (Forum) by BB11 on Wed, Jan 23 2013
  • Query in Naming in schematic and layout
    Hello    I have a question regarding naming conventions in layout and schemtics. Suppose I use vdd! and vss! to represent in my layout for vdd and gnd. When i run a testbench simulation, i assign the local value vdd! to the master value vdd. But i still see that my ouput is not as expected. Could anyone help me with this? Thanks ...
    Posted to Custom IC Design (Forum) by BB11 on Fri, Jan 18 2013
Page 1 of 1 (2 items)