Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (1 items)
  • Continue after failed PSL assertions
    Hi! I am running a mixed-language simulation with irun. This includes PSL assertions in my VHDL code and SVA assertions in my SystemVerilog/UVM testbench. As the simulation runs in non-interactive mode on a cluster, I do not want the simulation to stop due to failed assertions. It rather should log it in the database and continue. But the ...
    Posted to Functional Verification (Forum) by wltr on Wed, Dec 12 2012
Page 1 of 1 (1 items)