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 Community Search 

Page 1 of 4 (36 items) 1 | 2 | 3 | 4 | Next >
  • Error in MMSIM when executing on 64bit machine
    Hi, I am getting following error while executing spectre simulation from a 64 bit machine.  Can't load '/IC_TOOLS/CADENCE/MMSIM111/tools.lnx86/mdl/etc/perl/cdsPSF.so' for module cdsPSF: libelf.so.1: cannot open shared object file: No such file or directory at ...
    Posted to Custom IC Design (Forum) by Arslan on Thu, Jun 27 2013
  • problem with sense amplifier detection in ELC
    hi all, I am trying to generate .lib for the standard configuration of sense amplifier using encounter library characterizer. but following error appears after db_prepare -f commnad: ==============================       DESIGN : CHAPPEL_CKT ============================== - analog node : NMOS_DRAIN - removed pull-up ...
    Posted to Digital Implementation (Forum) by Arslan on Fri, Jun 14 2013
  • Spice syntax error in ELC
    HI all, I am using encounter library characterizer to make .lib, I have designed an inverter as a test case and given its spice netlist to elc alongwith model file of tsmcN28. now when i laucnh elc and load database using db_open command, database is loaded. but when I type the command db_prepare -f , it first loads models, then loads models as ...
    Posted to Digital Implementation (Forum) by Arslan on Fri, Jun 7 2013
  • error in creat_generated_clock
    HI, I have a design in which I have to create a generated clock and then use this generated clock to create another clock...Encounter gives error and does not recognize the first generated clock which would be used to generate second generated clock. Any suggestions?
    Posted to Digital Implementation (Forum) by Arslan on Thu, May 9 2013
  • holdTargetSlack has no effect
    Hi all. I have a design in which a positive edge triggered flip flop is connected to negative enable latch. both flip flop and latch have same clock (f=2.4GHz). now I am passing this design through encounter and I have given following tcl as always source plugin setOptMode -holdTargetSlack 0.15 setOptMode -setupTargetSlack 0.15 problem is that ...
    Posted to Digital Implementation (Forum) by Arslan on Thu, Apr 25 2013
  • Equal Rise/Fall delay
    Hi, how to enforce encounter to use those standard cells only whose rise/fall delay is equal?
    Posted to Digital Implementation (Forum) by Arslan on Sun, Apr 21 2013
  • Beta Ratio Standard Cells
    hi, is there any method to enforce encounter to use certain beta ratio standard cells from a library ... ?
    Posted to Digital Implementation (Forum) by Arslan on Sun, Apr 21 2013
  • netlist import failed...
    Hi, I have a verilog netlist as follows module XYZ   (    input a,    input b,    output [12:0] y    ) ;   OR2_X1M_A12TH_C35 g67 [12:0] ( .A(a), .B(b), .Y(y) ) ;  endmodule   when i import it using import design form in encounter v12 following error occurs **ERROR: ...
    Posted to Digital Implementation (Forum) by Arslan on Fri, Apr 5 2013
  • Re: how to set `ifdef switch`
     Thanks Andrew, it works. -Arslan
    Posted to Custom IC Design (Forum) by Arslan on Tue, Apr 2 2013
  • Crosstalk analysis
    Hi, How crosstalk analysis can be performed for a custom digital design whose layout has been made in virtuoso.?
    Posted to Custom IC Design (Forum) by Arslan on Thu, Mar 28 2013
Page 1 of 4 (36 items) 1 | 2 | 3 | 4 | Next >