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 Community Search 

Page 1 of 1 (3 items)
  • Re: Average power calculation
     Hi Sagar, While simulating 16 bit RCA in virtuos Analog Design environment window select OUTPUT ..> saveall. In save all options enable all options. Run simulation. In waveform window select Browser..> results...> open results    , then Select Waveform Data base window will open ,here select psf file. In left side of ...
    Posted to Custom IC Design (Forum) by Gangadhar Redd on Thu, May 2 2013
  • Re: Fingers and multiplier of MOSFET
    Multiplier - number of Parallel MOS devices Finger Width - width of each gate finger/stripe Fingers - number of poly gate fingers/stripes used in layout
    Posted to Custom IC Design (Forum) by Gangadhar Redd on Fri, Apr 12 2013
  • Export LEF via problem
     Hi , While I trying to export .lef file from Cadence virtuoso 6.1.5 version , I got the following error "ERROR: (OALEFDEF-50138): VIA Via56_stack_west: Failed to open master view - Open of gpdk180/Via56_stack_west/symbolic failed - cellView for the design was not found - Ensure that the via is correctly defined in the technology ...
    Posted to Mixed-Signal Design (Forum) by Gangadhar Redd on Wed, Dec 19 2012
Page 1 of 1 (3 items)