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  • Trouble with reading vcd file in RC 11.2
    Hi,   I used Xilinx ISE to generate .vcd file for my design and then read it in RC 11.2 in order to estimate power consumption. I got the following report: --------------------------------------------------------------- Asserted primary inputs in design         : 99 (100.00%) Total connected primary inputs in design ...
    Posted to Logic Design (Forum) by Chongxi on Tue, Nov 20 2012
Page 1 of 1 (1 items)