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 Community Search 

Page 1 of 3 (27 items) 1 | 2 | 3 | Next >
  • Re: Issue with DRC - "run is invalid"
    Nope, the only thing containing "?out" in both .rsf and .rul files is: ?outputErrorLib t Regards.
    Posted to Custom IC Design (Forum) by apaj on Thu, May 1 2014
  • Re: Issue with DRC - "run is invalid"
     Hello Quek, the command you mention, does not exist in DRC Run window nor in .rul file. Did you maybe mean ?outErrorLayers avParameter?  Because that one appears, but - it has been disabled all along (Use in Run unchecked). Also, the option Store all error layers to a gds file has also been disabled all along. The only one of ...
    Posted to Custom IC Design (Forum) by apaj on Thu, May 1 2014
  • Re: Issue with DRC - "run is invalid"
    Hello Quek. I looked for that variable in my .rsf file, but no such thing exist - so, I should be looking somewhere else, probably. Could you be more specific, please? Regards.  
    Posted to Custom IC Design (Forum) by apaj on Thu, May 1 2014
  • Re: Issue with DRC - "run is invalid"
     Hm... Somehow I completely neglected your last sentence... I just saw that you are telling me to open the run manually in the end. And yes... I do get the Error Layer Window - thank you very much! But, since we are already here - what do you think, why does any of this happen? I mean, why not open it normally? Also, rereading my post, I ...
    Posted to Custom IC Design (Forum) by apaj on Thu, May 1 2014
  • Re: Issue with DRC - "run is invalid"
    Thank you for your time and effort. I had already tried creating a new folder and choosing it as a Run Directory - the result was the same ("run invalid"). Now, the other thing you mentioned gave some feedback. I saved drc.rsf in the folder from which I run icfb (correct or shoud I have chosen a different place?) and run your command. ...
    Posted to Custom IC Design (Forum) by apaj on Thu, May 1 2014
  • Issue with DRC - "run is invalid"
    Hello, when I try to run BEOL DRC everything seems to be in order. I don't get any errors, Assura successfully loads .rul and .rsf files, and .log file keeps feeling up normaly. I see all the errorchecks being performed and in the end I get "Assura terminated successfully!" message. Nevertheless, it asks me whether I want to see ...
    Posted to Custom IC Design (Forum) by apaj on Wed, Apr 30 2014
  • Custom coil design
    Hello. We would like to try to create a coil of a different topology for a given technology. In other words, the technology I am working with offers a regular spiral inductor. We are interested to see how would a coil of different metal structure behave.  Is there a way for me to draw something in Layout XL and than make it a new device? ...
    Posted to Custom IC Design (Forum) by apaj on Tue, Apr 22 2014
  • Re: Help me with the tool to do corner analysis ...
    Hello. If I may interfere - I had the same issue when I started, about a year or so ago. Eventually, we came to a conclusion that this tool does not really work that well, so we abandoned it. Thanks to a colleague we didn't do it by force - we took a larger hammer, as Murhpy would say. Anyway, what was done is that we included all the paths ...
    Posted to RF Design (Forum) by apaj on Thu, Apr 10 2014
  • Re: HBAC analysis issue, while simulating a mixer from Cadence examples
    Thank you for your time. I don't have a IC6 installation, but I will check with a colleague. Thank you for your effort. Regards.
    Posted to RF Design (Forum) by apaj on Thu, Apr 10 2014
  • Re: HBAC analysis issue, while simulating a mixer from Cadence examples
     Hello. Thank you for a through explanation and sorry for a late answer - some paperwork needed to be taken care of. I ventured into the rfLib folder and there I found both balun and balun_ideal. Each of these has two folders (symbol and veriloga) and prop.xx. The symbol folders for each look the same: they both contain a master.tag file ...
    Posted to RF Design (Forum) by apaj on Thu, Apr 10 2014
Page 1 of 3 (27 items) 1 | 2 | 3 | Next >