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 Community Search 

Page 1 of 2 (11 items) 1 | 2 | Next >
  • Multi Mode synthesis v/s Multi Corner synthesis
     hi,   i just have a simple question that whether RC tool goes for Multi mode synthesis and multi corner synthesis at the same time or not ? Likewise do we need to do any settings on the same for both the synthesis to take place at the same time or not ? what all settings are required to go for both type of synthesis if we do it ...
    Posted to Logic Design (Forum) by tanyacool on Mon, Feb 18 2013
  • no constraints on hierarchial boundaries
     hi, this is the question related to RC tool, where i do not want to specify any constraints on the hierarchial boundaries of my design. how do i proceed doing the same.   thanks tanyacool  
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • How do we exclued delay cells in RC
     hi , i have thi s query regarding RC tool, as to how will the tool be able to exclude the delay cells in a design during synthesis.   thanks tanyacool
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • Re: Rtl Compiler behaviour on clock
    hi grasshopper,  i got your point and i strongly agree with you. But what i need is if this is the case present already in our design then will the tool still use clock as a data pin as you have mentioned above. what my question was is there any way by the tool to avoid the use of clock as a reset pin or a data pin or it totally depends ...
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • Rtl Compiler behaviour on clock
     hi,  i had the doubt regarding the fact that how we can prevent the use of clock pin as a reset pin or a data pin. do we need to do some changes in the SDC file or some attribute settings in the main rc script.   thanks  tanvyacool
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • max_fanout constraint
     hi, i Wanted to know as to when we set this command in the sdc file, where does this command saffects the whole design. Whether it effects the timing, area or power of the whole design. Suppose if i set set_max_fanout =10 and next i set it to 15, what will be affected with this change? How does a designer decides as to what should be the ...
    Posted to Logic Design (Forum) by tanyacool on Tue, Nov 6 2012
  • Re: dft settings during DFT scan insertion
     hi gh,  let me frame the question in a different way: do we need testability logic to be inserted if we are only going for scan insertion. i am trying to do muxed scan style insertion and after that i checked the DFT rules, where around 43% registers were passing and after that i did connect scan chains in order to connect it, but i ...
    Posted to Logic Design (Forum) by tanyacool on Mon, Oct 29 2012
  • dft settings during DFT scan insertion
     hi,  i am totally new to DFT and using RC tool for scan insertion. Some attributes settings needs to be done during synthesis. can anyone please list them out for scan insertion settings.   thanks  tanya
    Posted to Logic Design (Forum) by tanyacool on Mon, Oct 29 2012
  • Re: Wanted to know the behaviour of RC on different SDC command
    hi grasshopper,  i just cross checked again with my designregarding the SDC written, the mistake was on my end as the memory.v was also being fed to Spyglass tool, so it was throughing the error, but the SDC which i was writting manually did not have the memory module so it was passing.   Thanks for the ...
    Posted to Logic Design (Forum) by tanyacool on Thu, Oct 18 2012
  • Wanted to know the behaviour of RC on different SDC command
     This is something very unusual regarding the behaviour of RC on different SDC commands provided to it. I had 2 sdc of the same design: One sdc was which i had written it manually Second one was the SDC generated by Spyglass tool. The interesting thing to be noted here was that with the first SDC file, the tool was showing no error in the ...
    Posted to Logic Design (Forum) by tanyacool on Wed, Oct 17 2012
Page 1 of 2 (11 items) 1 | 2 | Next >