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 Community Search 

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  • where can we get the RAK
    hi ,    From where can we download the RAK for different tool on Mac OS. Please let me know.   Thanks Tanya 
    Posted to Logic Design (Forum) by tanyacool on Tue, Sep 10 2013
  • Re: Library requirements during elaboration stage
     Hi Grasshopper,   Thanks for the reply, so a more basic question on that which i would like to raise is that leave behind the macros and other cells which are to be instatntiated, let us take an example of the actual logic which needs to be synthesized.  In that case also do we still require the libraries before the elaboration ...
    Posted to Logic Design (Forum) by tanyacool on Tue, Aug 20 2013
  • how to define scan chains in RC
     Hi,   How to define the scan chains in RC and how to prevent the broken chains . Tha basic question points to on how prevent the scan inputs of the scanable flops to get not tied up to 0.   Thanks  Tanyacool
    Posted to Logic Design (Forum) by tanyacool on Tue, Aug 20 2013
  • Library requirements during elaboration stage
     Hi I have a very basic question regarding the whole synthesis process.  We say that before mapping the whole process goes technology independent (library), only during mapping it is technology dependent. My question is then why do we have to source the libraries before the elaboration step which comes before the mapping ...
    Posted to Logic Design (Forum) by tanyacool on Tue, Aug 20 2013
  • Multi Mode synthesis v/s Multi Corner synthesis
     hi,   i just have a simple question that whether RC tool goes for Multi mode synthesis and multi corner synthesis at the same time or not ? Likewise do we need to do any settings on the same for both the synthesis to take place at the same time or not ? what all settings are required to go for both type of synthesis if we do it ...
    Posted to Logic Design (Forum) by tanyacool on Mon, Feb 18 2013
  • no constraints on hierarchial boundaries
     hi, this is the question related to RC tool, where i do not want to specify any constraints on the hierarchial boundaries of my design. how do i proceed doing the same.   thanks tanyacool  
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • How do we exclued delay cells in RC
     hi , i have thi s query regarding RC tool, as to how will the tool be able to exclude the delay cells in a design during synthesis.   thanks tanyacool
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • Re: Rtl Compiler behaviour on clock
    hi grasshopper,  i got your point and i strongly agree with you. But what i need is if this is the case present already in our design then will the tool still use clock as a data pin as you have mentioned above. what my question was is there any way by the tool to avoid the use of clock as a reset pin or a data pin or it totally depends ...
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • Rtl Compiler behaviour on clock
     hi,  i had the doubt regarding the fact that how we can prevent the use of clock pin as a reset pin or a data pin. do we need to do some changes in the SDC file or some attribute settings in the main rc script.   thanks  tanvyacool
    Posted to Logic Design (Forum) by tanyacool on Wed, Jan 16 2013
  • max_fanout constraint
     hi, i Wanted to know as to when we set this command in the sdc file, where does this command saffects the whole design. Whether it effects the timing, area or power of the whole design. Suppose if i set set_max_fanout =10 and next i set it to 15, what will be affected with this change? How does a designer decides as to what should be the ...
    Posted to Logic Design (Forum) by tanyacool on Tue, Nov 6 2012
Page 1 of 2 (15 items) 1 | 2 | Next >