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  • Strange "out of memory" error during verilog import
    Hi,   I am trying to save myself the pain of connect 300+ pins by importing a verilog file instead. But I got the following error. Can anyone shed some light on this? I cannot find anything on documentation nor Google.    @(#)$CDS: ihdl.exe version 5.1.0 01/27/2011 00:14 (cicln04) $  Tue Oct  9 09:32:34 2012 Verilog ...
    Posted to Custom IC Design (Forum) by asimecs on Tue, Oct 9 2012
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