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 Community Search 

Page 1 of 1 (4 items)
  • Re: Gate Level Sim - SDF annotation debug
    Found the issue. My run script had inherited a '-delay_mode unit' switch which for some reason meant that Incisiv knew nothing about the timing checks. The warnings make sense when you know the solution but they're not very helpful during debug. Problem solved! Andy
    Posted to Functional Verification (Forum) by andymont on Wed, May 29 2013
  • Gate Level Sim - SDF annotation debug
    Hi,  I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour. When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment ...
    Posted to Functional Verification (Forum) by andymont on Thu, May 23 2013
  • Re: Tracking regression results with an SQLITE database
    Hi Steve,   Thanks for the quick reply. I obviously don't want to have to write a parser if I don't need to , is there a good way to export the information from the vmanager API ?  What I don't want to have to do is keep vsofs from every regression or indeed to keep regression data from every run. If I can export the ...
    Posted to Functional Verification (Forum) by andymont on Tue, Jan 15 2013
  • Tracking regression results with an SQLITE database
    Hi ,  I would like to keep track of the verification status of my project (verilog/systemverilog) coverage and pass/fail status of tests during the life of the project. Ideally I want to create an SQLITE database to keep track of this since SQLITE is stored in a file which can be archived with the project after tapeout. I am already writing ...
    Posted to Functional Verification (Forum) by andymont on Tue, Jan 15 2013
Page 1 of 1 (4 items)