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 Community Search 

Page 1 of 1 (6 items)
  • Brad Griffin Speaks at DesignCon - Give Him a Listen!!
    If you were not lucky enough to be atDesignCon this week, and many of us were not!  You might be interested in the streaming interviews posted on line.  Click here for link. Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's advanced node ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Thu, Feb 5 2009
  • 3D IC or TSV: The Next Phase in Functional Density and Miniaturization
    It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD Source and written by the popular long time ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Thu, Jan 22 2009
  • TSV, mainstream or niche?
    I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization.  I have heard several companies (foundries and some iDM's) talking about pilot projects in this area, but will it really ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Wed, Sep 24 2008
  • Analog/RF chip designers don't care about the Package?
    So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!!  Now I kinda understand that this could be true for chips that go into ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Mon, Aug 25 2008
  • Breaking down the 'virtual' wall
    In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies -- and more than a handful of leading IC companies -- have started programs to try and bring the ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Wed, Aug 20 2008
  • Verifying multi-technology chips-in-a-SiP, fact or fiction?
    With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?" If you have ever pondered this challenge, or have tried and failed, or tried and suceeded you ...
    Posted to IC Packaging and SiP (Weblog) by Keith Felton on Wed, Aug 20 2008
Page 1 of 1 (6 items)