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 Community Search 

Page 1 of 1 (5 items)
  • Viewing dynamic objects in the Simvision waveform window
    Hi All, I'm having trouble displaying the value of class data members in a Simvision waveform window (currently using version 12.10-s006). I'm using irun interactively to run my simulations, so I invoke irun with the following options: irun -gui -access +rwc -linedebug ...etc My testbench is UVM based so I use the UVM factory to build ...
    Posted to Functional Verification (Forum) by SCollins on Wed, Oct 17 2012
  • Re: SystemVerilog modport question
    Hi Steve, Thanks for responding, your workaround seems a good solution, however, I'm having problems elaborating my example design when I use a generate statement to create the slave sub-interface instances. My code for a slave is: module slave (slave_sub_if port); <slave code> endmodule  In my top level where I instantiate ...
    Posted to Functional Verification (Forum) by SCollins on Fri, Sep 28 2012
  • Re: Use of a specify block within a SystemVerilog interface
    I have since found out that IEEE Std 1800 (SystemVerilog LRM) does not allow specify blocks to be defined in interfaces. Also, Incisive does not currently support the use of hierarchical references in specify blocks.
    Posted to Functional Verification (Forum) by SCollins on Wed, Sep 26 2012
  • Use of a specify block within a SystemVerilog interface
    Hi All,  I'm currently converting a legacy testbench to use SystemVerilog interfaces between the DUT and some behavioural models. The testbench code includes a specify block that uses the $width system task to check for glitches on a signal between the DUT and one of the models. I've tried to update the code so that the $width task ...
    Posted to Functional Verification (Forum) by SCollins on Wed, Sep 26 2012
  • SystemVerilog modport question
    Hi All, I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the ...
    Posted to Functional Verification (Forum) by SCollins on Thu, Sep 13 2012
Page 1 of 1 (5 items)