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 Community Search 

Page 1 of 2 (18 items) 1 | 2 | Next >
  • The Future of OVM, VMM, and UVM
    In my last blog, I took a look back at the history of how we got to the first delivery of UVM. Now, let's take a look forward.  Over the past week since UVM was released, and Cadence opened the UVMWorld portal to support the new UVM Community and ecosystem, I have seen a number of customers asking questions about when to move to UVM as ...
    Posted to Functional Verification (Weblog) by Michael Stellfox on Mon, May 24 2010
  • UVM - 10 Years in the Making ...
    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM).  This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology.  While there has been a lot of hard work by many ...
    Posted to Functional Verification (Weblog) by Michael Stellfox on Mon, May 17 2010
  • Re: Verilog, System Verilog and SystemC
    What do  you mean by testing using Verilog? What differentiate the test and verify? In Verilog, you can write procedural code to define tests to stimulate and check your design.  This is a manual process since you have to think of each test, and then write the stimulus and check the expected behavior.  This is a way to ...
    Posted to Functional Verification (Forum) by Michael Stellfox on Thu, Sep 3 2009
  • Re: Verilog, System Verilog and SystemC
     Hi Jasonkee111, Good questions.  As you have discovered there are many languages available for design and verification with various advantages/disadvantages.  I will try to give you some recommendations based on my experience working with many customers. For RTL design, Verilog is still the main language being used today ...
    Posted to Functional Verification (Forum) by Michael Stellfox on Wed, Sep 2 2009
  • RE: regarding e ports
    Hi Krishna, I am pretty sure simple ports existed in Specman 4.3.1.  You might be setting the record for using the oldest version of Specman since 4.3.1 is about 6 years old.  Is there any reason why you can’t upgrade to the latest version, 8.2? Mike
    Posted to Functional Verification (Forum) by Michael Stellfox on Thu, Apr 16 2009
  • The OVM extended to support e and SystemC
    In case you missed the press release, the Open Verification Methodology (OVM) has been updated to support e as well as SystemC:  http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=022309_extended_ovm  The first implementation of OVM was for SystemVerilog back in 2007.  This donation from Cadence extends it to ...
    Posted to Functional Verification (Forum) by Michael Stellfox on Wed, Feb 25 2009
  • "...Yes, Virginia there is a Specman"
    I usually try to visit many of our customers in Europe (and other parts of the world) at least a couple of times a year.  On my last trip in October, while I was in Stockholm, I ended up having beers at a pub with one of our local AEs and a Specman customer.  This customer had been telling me about all the "good stuff" that he ...
    Posted to Functional Verification (Weblog) by Michael Stellfox on Mon, Feb 2 2009
  • RE: RE: RE: Temporal expression in e
    First, I would read the “N” signal value to a simple_port and use the simple_port in your temporal expression.  Below, I assume that the “N” signal value will not change during the evaluation of the temporal expression, and then I think this will work: extend sys ...
    Posted to Functional Verification (Forum) by Michael Stellfox on Fri, Jan 16 2009
  • RE: RE: Temporal expression in e
    Ok, then you need one temporal expression to capture the case when @a and @b occur on the same cycle, as well as the case when the don’t occur on the same cycle.  See below – I think this will work for you. expect (@a and @b)@clk or ((@a and not @b) => {eventually @b})@clk; Mike
    Posted to Functional Verification (Forum) by Michael Stellfox on Thu, Jan 15 2009
  • RE: Temporal expression in e
    Hi Spark, Can you write down the english expression of what you want to check?  It is not clear from your description below. Is this what you want to check: If event a occurs, then b must occur on the same cycle as a or any number of cycles after a Or do you need to check something else?? Mike
    Posted to Functional Verification (Forum) by Michael Stellfox on Wed, Jan 14 2009
Page 1 of 2 (18 items) 1 | 2 | Next >