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 Community Search 

Page 1 of 2 (17 items) 1 | 2 | Next >
  • Re: Virtuoso - Wire Bus Connectivity Issue
     yes thank you. it works.I didn't tag the bus wire. 
    Posted to Custom IC Design (Forum) by sohaiba on Mon, Feb 18 2013
  • Virtuoso - Wire Bus Connectivity Issue
    Hello,   I am facing this issue regarding how to connect the wire bus connection to the output connectors. If you look at the attached image below I have clearly named each bus bit to its output but I am still facing error.                     The screenshot image displaying ...
    Posted to Custom IC Design (Forum) by sohaiba on Sun, Feb 17 2013
  • Re: Export .tf into .lef file
     Moreover, also when I try to load technology file in virtuoso , following is displayed in CIW INFO (TECH-180006): Compiling class 'controls'.... INFO (TECH-180006): Compiling class 'layerDefinitions'.... INFO (TECH-180006): Compiling class 'layerRules'.... INFO (TECH-180006): Compiling class ...
    Posted to Custom IC Design (Forum) by sohaiba on Thu, Jan 3 2013
  • Export .tf into .lef file
     I have converted virtuoso .tf into lef file from file > export > LEF. But when I use it with encounter as a tech lef, there are a lot of  errors like the following **ERROR: (ENCLF-268):    " There is no spacing table defined bewteen cut class 'square' and 'square' in layer 'VIA6'. It ...
    Posted to Custom IC Design (Forum) by sohaiba on Thu, Jan 3 2013
  • How to use vcvs as an OR or AND gate
    Please can you elaborate how to use the vcvs source as OR or AND gate? How to connect the terminals?
    Posted to Custom IC Design (Forum) by sohaiba on Tue, Nov 27 2012
  • Hysteresis sweep option in DC
    Hi, I haven't been able to see a Hysteresis plot by using the DC Hysteresis sweep option. I have also enabled the 'DC operating point' option as well. I was expecting to find a negative going plot as well for the device but there is only a single Voltage transfer characteristic curve.  Following are the settings the Cadence ...
    Posted to Custom IC Design (Forum) by sohaiba on Thu, Oct 11 2012
  • Re: ViVa waveform tool
     Yes it is the same problem I mentioned in that post. Thank you your solution by selecting All(instead of LSW) and assigning colours to the y0 drawings etc has worked. Now the only issue is that after restarting Virtuoso the LSW is selected (instead of All) which is why the traces turn back to white again. How to stop this from reseting ...
    Posted to Custom IC Design (Forum) by sohaiba on Mon, Jul 30 2012
  • ViVa waveform tool
    Hello,  I am facing an issue during plotting the results in ADE-L simulation enviroment,the traces are always white in color. Even after installing the latest ISR12 hotfix for IC615 the issue remains the same. The most surprising part of this issue is that sometimes it automatically starts showing colours but that is very few times. I am ...
    Posted to Custom IC Design (Forum) by sohaiba on Mon, Jul 30 2012
  • Re: downgrading RHEL to support IC 5141
     Hello, Dear Andrew, Related to this update for IC615 you are talking about (ISR12), Are you talking about the hotfix IC6.1.5.500.1.2? I checked online, and its size was around 7gb. Is this hotfix going to update all of the base cadence files installed on my system? Would I need to redo all the setting that I have done for the base ...
    Posted to Custom IC Design (Forum) by sohaiba on Thu, Jul 26 2012
  • Re: IC.6.1.5 support for RHEL6.0
      MMSIM 11.1 was being supported because Cadence 5.1.6 check configuration showed that it was supported, hence I don't think spectre is old. When we used the checkSysConf , it shows an error that IC6.1.5 does not support RHEL 6.0 as its patch does not exist in the following directory path ...
    Posted to Custom IC Design (Forum) by sohaiba on Thu, Jul 19 2012
Page 1 of 2 (17 items) 1 | 2 | Next >