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  • Unwanted "X" coming during re-simulation with vector
    Hi, We are creating vectors with vcd files. If we re-run the simulation we are seeing few "X" on the signals which in turn causing simulation fail. Location of signal going "X" is, At the synchronizer input we are seeing logic high input for two clocks, for the first cycle synchonizer is able to give correct output but ...
    Posted to Functional Verification (Forum) by dhanash on Wed, May 30 2012
Page 1 of 1 (1 items)