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 Community Search 

Page 1 of 1 (6 items)
  • Re: Make macro block pin visible in higher hierarchy
    Maybe I should be more specific. These mentioned macro blocks are supposed to be TSVs (through silicon via). This is not possible in encounter, so I try to model this is 2D. In reality no wire excists between the two pins. This is why I want a direct connection, so I can leave the wiring delay out in my calculations.
    Posted to Digital Implementation (Forum) by Mikutine on Mon, Jul 22 2013
  • Make macro block pin visible in higher hierarchy
    Hello all, I have the following situation in SOC Encounter: I have made a design X, which uses some standard cells, and some macro blocks. One type of macro block should have an input or output port. This should also be an input or output port of the design X, but should not be connected to the side of the design X.  I want to utulise two ...
    Posted to Digital Implementation (Forum) by Mikutine on Thu, Jun 27 2013
  • Show slack per node in timing report soc encounter 8.1
    Hello, I have made a design, and after place&routing I want to study the timing report of the paths. This report I make trought the 'report_timing' command. With the -format, you can specify what information you want to see in the timing report. I want to see the slack per node in the report. So basically I want to see also a column of ...
    Posted to Functional Verification (Forum) by Mikutine on Mon, Mar 11 2013
  • Re: Importing a def file (made in encounter) into virtuoso.
    I tried to do what you've said, to make a new library with attaching the technology library 'NCSU_TechLib_FreePDK45' and then import the LEF file with only the via information. Well, I did that, and I get the following errors: 'Constraint validRoutingVias does not match the referenced technology database'. I get a bunch of ...
    Posted to Custom IC Design (Forum) by Mikutine on Wed, May 30 2012
  • Re: Importing a def file (made in encounter) into virtuoso.
    Dear Alex, Basically, I understand what you are trying to say. But I think there is a misunderstanding. As far as I know, the via information is in the standard cell library (Nangate OpenCellLibrary). This is the library that I've used to synthesize a design (in Synopsys Design Compiler) and place&route (in Encounter).  Now I want to ...
    Posted to Custom IC Design (Forum) by Mikutine on Fri, May 25 2012
  • Importing a def file (made in encounter) into virtuoso.
    Dear users, I've made a design in Encounter with the Nangate OpenCell Library. Everything is placed and routed, and I have extracted the def file. I want to use that def file, so I can import it in Virtuoso, because I have to add some shape pins in there. The first thing I did, is make an new library, where I attached the technology file ...
    Posted to Custom IC Design (Forum) by Mikutine on Tue, May 22 2012
Page 1 of 1 (6 items)