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 Community Search 

Page 1 of 3 (26 items) 1 | 2 | 3 | Next >
  • settings for Verilog Import
    Hi, Is there a setting in the VerilogIn to include the POWER_PINS during the schematic creation? `timescale 1ns/1ps `celldefine `ifdef POWER_PINS module Std_cell_def (Y, A, B, C, VDD, VSS); inout VDD; inout VSS; supply1 VDD; supply0 VSS; `else module Std_cell_def (Y, A, B, C); `endif output Y; input A, B, C;   specify     // ...
    Posted to Custom IC Design (Forum) by navi2582 on Tue, Oct 1 2013
  • Re: IC5141 CDL in skipping passive devices
     I think you may have to include the following at the beginning of your cdl netlist: .PARAM *.BIPOLAR *.RESI = 1 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.SCALE METER
    Posted to Digital Implementation (Forum) by navi2582 on Mon, Jul 8 2013
  • Triggering callbacks on specific devices
    Hi, I am using "CCSinvokeCdfCallbacks.il"  and "CCSCdfCallbackEntireLib.il" skill procedures to trigger callbacks on a entire library, running with the following options, -->CCSinvokeCdfCallbacks(cv ?callInitProc t ?useInstCDF t ?order list("l" "w")) With this, the callback functions are applied ...
    Posted to Custom IC SKILL (Forum) by navi2582 on Wed, Jun 19 2013
  • CDLin pin/net mismatch
    Hi, I am having a CDL netlist with information: *.GLOBAL VDD:p, GND:g *.PIN VDD:B, GND:B and when I CDLin, both symbol and schematic views have pin/signal names as VDD!/GND! instead of VDD/GND. I do not want VDD/GND suffixed with ! in my cell views. Is there a way to achieve this? Thanks in advance...
    Posted to Custom IC Design (Forum) by navi2582 on Thu, Apr 18 2013
  • lvsIgnore of voltage source vdc
    Hi, I have a legacy voltage source "vdc" in IC614 env, modified long time ago (set lvsIgnore to FALSE) and still works fine (gets netlisted during CDL). But, followed the same procedure (copied "vdc" from analogLib to my local directory, modified the lvsIgnore to FALSE in the symbol view) in IC615 env andit doesn't work ...
    Posted to Custom IC Design (Forum) by navi2582 on Thu, Apr 4 2013
  • Specman error while running ENET VIP
     Hi, I am getting the following specman related error. Modified the $PATH variable accordingly but of no use. Any ideas from anyone? Thanks, Naveen Here is the run.log file: ************************************ SEED=30561 Copying /MENTOR/install/modelsim_se_10.0c_2011_08/modeltech/linux/../modelsim.ini to modelsim.ini Modifying ...
    Posted to Functional Verification (Forum) by navi2582 on Wed, Apr 3 2013
  • Re: schematic licenses usage
     Thanks Andrew for the confirmation!!
    Posted to Custom IC Design (Forum) by navi2582 on Thu, Jan 24 2013
  • schematic licenses usage
    Hi, Recently we found that in order to do LVS or RCX run using calibre, a schematic license is required  for exporting the cdl netlist. Do we need to have a schematic license available in order to run LVS or RCX? Is there any option we can set to successfully export the cdl netlist without the need of the schematic license? Thanks
    Posted to Custom IC Design (Forum) by navi2582 on Wed, Jan 23 2013
  • Re: RE: ADE XL doesn't run
    Hi Abdel, I was able to figure out how to run the ADE XL (but it's not the ideal solution). Since you are using the same version of virtuoso, it might work for you as well. Create a new directory with "cds.lib" and launch virtuoso (as shown below). Ex: ********************************************** -->cadence (current ...
    Posted to Custom IC Design (Forum) by navi2582 on Thu, Oct 18 2012
  • Re: difference between LD_LIBRARY_PATH and PATH
    Yes. It did answer my question. Thank you. Regards, Naveen
    Posted to Custom IC Design (Forum) by navi2582 on Tue, Jul 3 2012
Page 1 of 3 (26 items) 1 | 2 | 3 | Next >