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 Community Search 

Page 1 of 1 (6 items)
  • Auto metal fill using calibre
    Hi folks,I am working on a 28nm project, which requires auto metal fill for our chip. After googling, I know that Calibre is able to do auto metal fill. But I have not found any commands or scirpts concerning how to do this. Can you give me a hint or any comments about using Calibre. Plus, Calibre SmartFill can do this as well, but we have no such ...
    Posted to Custom IC Design (Forum) by cupidsd on Mon, May 28 2012
  • Clock tree design
    Hi,We are designing a basic clock tree for a chain of flip-flops. The method that we are using is logic effort. Since the clock tree is just a bunch of inverters, G=1. So we only need to find out H (electrical effort), which is equal to Cout/Cin.Here, Cout is the input capacitance of the flip-flop, which could be derived from the faundry's ...
    Posted to Custom IC Design (Forum) by cupidsd on Mon, May 28 2012
  • clock tree design
    Hi, We are designing a basic clock tree for a chain of flip-flops. The method that we are using is logic effort. Since the clock tree is just a bunch of inverters, G=1. So we only need to find out H (electrical effort), which is equal to Cout/Cin. Here, Cout is the input capacitance of the flip-flop, which could be derived from the ...
    Posted to Logic Design (Forum) by cupidsd on Thu, May 24 2012
  • how to find out gate capacitance
    Hi,  We are designing a chip using 28nm design kit. we need to find out the gate capacitance of transistors, but the problem is how to find out these values. I looked through the kits technology documents, there is no such information seemingly.   Thanks a lot.
    Posted to Custom IC Design (Forum) by cupidsd on Thu, May 24 2012
  • Re: TAP cell in 28nm Kit
    Thanks  a lot, Quek. Thats what i ususally do, trial and error. :) But the issue for me is i did not find any TAP cells. Actually I have no idea what these cells look like. I found a layer named TAP, which is like METAL1. Its only a layer, so how to use it in our design? If its only a layer, how does it work, im quite curious. Thanks ...
    Posted to Custom IC Design (Forum) by cupidsd on Wed, Apr 25 2012
  • TAP cell in 28nm Kit
    We are designing a 28nm test chip, but right now we run into a problem about tap cells. In order to make a good ohmic contact for wells, we usually add well contacts, which requires additional active regions. But this is not the case in 28nm. Instead, tap cells are recommended. But I do not know the max distance between these tap cells, and how to ...
    Posted to Custom IC Design (Forum) by cupidsd on Wed, Apr 25 2012
Page 1 of 1 (6 items)