Re: very long bit pattern for vbit source
Do you need a specific bit pattern, or would a psudeo random bit pattern be OK?
I created a verilog-A module which generates a PRBS 2^15 - 1 bit pattern.
Bit period can be set via a clock input signal, or with a verilog-a "timer" event generator.
Output amplitude can be set by a parameter, or by pwr/gnd input pins.
Hope this ...