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 Community Search 

Page 1 of 1 (5 items)
  • Re: LVS LAYOUT debug?!
    The first thing I noticed is that the body connections do not match between schematic and layout. You may need to change the schematic. Tony
    Posted to Custom IC Design (Forum) by TonySal on Tue, Nov 12 2013
  • Relative include path for a vpwlf source
    I'm runing a spectre simulation via ADE-L in 6.1.5 I want to use a VPWLF signal source, and I would like to point to the file with a directory path which is relative to my cadence startup directory (i.e. my design workspace). All the documentation I have read talks about directory paths which are relative to the netlist directory, but this ...
    Posted to Custom IC Design (Forum) by TonySal on Thu, May 16 2013
  • Re: veriloga model not being found
    Based on the error message, you are using the cell name "CNTfet". In the veriloga code, did you change the module name to "CNTfet" ? Good luck, Tony
    Posted to Custom IC Design (Forum) by TonySal on Wed, Nov 14 2012
  • Re: very long bit pattern for vbit source
    Do you need a specific bit pattern, or would a psudeo random bit pattern be OK? I created a verilog-A module which generates a PRBS 2^15 - 1 bit pattern. Bit period can be set via a clock input signal, or with a verilog-a "timer" event generator. Output amplitude can be set by a parameter, or by pwr/gnd input pins.  Hope this ...
    Posted to Custom IC Design (Forum) by TonySal on Wed, Nov 14 2012
  • Saving verilog-A variables in UltraSim
    I am trying to debug a verilog-A behavioral model, using UltraSim as my simulator. How do I tell UltraSim to save the internal variables in my model, so I can view/plot them? In Spectre there is an option saveahdlvars=all, but it does not seam to work in UltraSim.
    Posted to Custom IC Design (Forum) by TonySal on Sat, Feb 20 2010
Page 1 of 1 (5 items)