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Page 1 of 1 (2 items)
  • Generation of EVCD file for Verilog-AMS
    Hi,   Testbench developed in verilog-AMS and uses wreal as a ports and internal signals. When It's tried to generate EVCD for design ports with $dumpports() gives error related to "Wreal is not supported". I am using IUS 10.2 version. I need EVCD for vector generation for tester.   Please help me out. Thanks in ...
    Posted to Functional Verification (Forum) by Anky on Tue, Sep 25 2012
  • System Verilog and AMS
    Hi All, Which tool is supporting system verilog and ams both togather? I am using IUS 10.20-s106 and getting error as below: ncvlog: *F,AMSASV: The -ams and -sv options cannot be used together.  Please help me out. Regards, Ankit
    Posted to Functional Verification (Forum) by Anky on Mon, Apr 2 2012
Page 1 of 1 (2 items)