Home > Community > Search

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Community Search

Find results with all the words
Matching all the tags
Written by
Scope

Page 1 of 1 (5 items)

Re: custom inductor/tline layout Assura LVS issue
I figured this out, the cause is that pinLayer definition in extract.rul is missing, the file require a few edits, relevant informantion can be found in Assura Developer Guide. Thanks for your attention. If you have trouble with this too, I'd be gald to help out. Ran

Posted to RF Design (Forum) by snaildr on Wed, May 2 2012
custom inductor/tline layout Assura LVS issue
Hi there, I need to incorporate a few custom designed transmission lines and inductors in to a TSMC 65nm tapeout. I found a document from another TSMC pdk about using Assura ?blackboxcell option to do LVS and RCX. The basic procedure is that you copy n2port element into the PDK lib and name it as a new cell (for example n2port_d1). ...

Posted to RF Design (Forum) by snaildr on Mon, Apr 30 2012
Re: ASSURA LVS error | Custom Inductor | Pin mismatch | Unbound devices
Hi Pitter, Quek Have you figured out about the pin errors? I ran into the same problem... Thanks, Ran

Posted to Custom IC Design (Forum) by snaildr on Mon, Apr 30 2012
Re: trouble with getting correct ro through sp analysis in spectre
Issue resolved, I was looking at Z22 to get the port2 input impedance, but Z-parameter is really Z-parameter not (s11+1)/(1-s11). So, to get the port input impedance one should look at ZM parameter or equivalently the Z-smith of S-parameter. Thanks Tawna for your kind reply. thanks, Ran

Posted to RF Design (Forum) by snaildr on Thu, Mar 29 2012
trouble with getting correct ro through sp analysis in spectre
Hi there, I'm pretty new to Spectre, and was simulating some basic stuff. Here's a question about getting ro using sp analysis that puzzls me. I'm under the impression that for the drain-source impdance, the large signal value is 'ron' which is Vds/Id, and the small-signal value is ro==1/gds, which is dVds/dId. So, for ...

Posted to RF Design (Forum) by snaildr on Sat, Mar 24 2012

Page 1 of 1 (5 items)

Email

Share

Subscribe

Contact Us

Community Search