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 Community Search 

Page 1 of 2 (13 items) 1 | 2 | Next >
  • SystemC sc_method schedule
    Hi all,  I have a question about systemC sc_method schedule. In my work, event A will trigger sc_method A, event B will trigger sc_method B; and sc_method A and B both will modify a same global variable. My question is what if event A and B happens at the same time? which sc_method will be scheduled first? Can I control this schedule ...
  • extract memory value in systemC
    Hi all,  I have 2 files.  In file A.vhd, I model a memory using "type t_mem is array(conv_integer(BASE) to conv_integer(TOP-1)) of std_logic_vector(7 downto 0);     variable mem : t_mem;". In file B.cpp, I use "rtl_mem_value.observe_foreign_signal(memory_path)" to extract memory value, but I get ...
    Posted to Functional Verification (Forum) by jxker on Tue, Dec 11 2012
  • Re: question about SVA
    Hi all, I find the problem. I should add "-abvrecordcoverall" option in ncsim command line, this enables reporting of all finish counts for cover properties. And by default, IES reports one finish for each cover property instance.
    Posted to Functional Verification (Forum) by jxker on Mon, Apr 16 2012
  • Re: question about SVA
    Hi all, I think I made a mistake. I find that once "cover" hit for the first time, it will not check anymore. So in the coverage report, it just hit once. I want to know how to make it checking during all the simulation, so the covereage report will show how many times it hits. Thank you very much!
    Posted to Functional Verification (Forum) by jxker on Mon, Apr 16 2012
  • question about SVA
    Hi all, I write a vunit file with SVA, I want to check a var every negedge clk, but it seems that it just check on the first negedge. Can you help me please? following is my code:   "test_var" is a constant, and it always equals to 1 my command: ncvlog -sv -propfile vunit.v module_name.v;   ncelab -coverage ...
    Posted to Functional Verification (Forum) by jxker on Mon, Apr 16 2012
  • Re: question about PSL
    Hi, TAM1 Thank you for your help, you helped a lot. According to you advise, I think we should put the delay (#1) after "data" is assignment(data = cov_t.data_a), otherwise, the tenth assertion check(i = 9) will not be done.
    Posted to Functional Verification (Forum) by jxker on Sun, Apr 8 2012
  • question about PSL
    Hi, all: I want to do assertion check in a "for" loop, and I want to do assertion check in every loop(totally 10 times in my file), but it seems that the assertion check only done once, and at the very beginning of the file instead of after going into the loop.       ncsim shows "ncsim: *E, ASRTST ...
    Posted to Functional Verification (Forum) by jxker on Fri, Apr 6 2012
  • Re: question about transition coverage
    Hi yongchen, Thank you.
    Posted to Functional Verification (Forum) by jxker on Mon, Mar 26 2012
  • Re: question about transition coverage
    Hi yongchen, B(i) and B(i+1) are the same variable, but in two different time. According to you advise, I need to redord the previos value of B. Am I right?
    Posted to Functional Verification (Forum) by jxker on Mon, Mar 26 2012
  • question about transition coverage
    Hi, all: I have a question about transition coverage. I have two variables, A and B, A and B both have several values. If I want to do transition coverage on the condition below: bins[ ]  trans_cov: A(i) => A(i+1) iff ( B(i) <= B(i+1) ),  this means only when B changes to a larger value, I will do the transition ...
    Posted to Functional Verification (Forum) by jxker on Mon, Mar 26 2012
Page 1 of 2 (13 items) 1 | 2 | Next >