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Page 1 of 3 (28 items) 1 | 2 | 3 | Next >
  • Re: CDR for USB 3.0 PHY
    Sir, First of all I would like to thank you for your quick reply and also its been a very fruitful advice. Regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Wed, May 28 2014
  • CDR for USB 3.0 PHY
    Sir,     I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic jitter using ...
    Posted to Custom IC Design (Forum) by Jithin on Tue, May 20 2014
  • Impedance measurement
    Sir/Madam,   I have been designing a Differential drive rectiifer for UHF passive RFID in 130nm CMOS process. As the design of rectifier completes I got stuck with the impedance measurement, i.e. for finding input impedance of rectifier using Cadence Virtuoso. As it is a non-linear circuit which simulation should I choose to find or how ...
    Posted to RF Design (Forum) by Jithin on Mon, May 12 2014
  • modelling reflection in Cadence Virtuoso
    Hello Sir, I have been trying to design a UHF passive RFID  tag in 130nm on Cadence Virtuoso IC 5.4.1. As for the design of a matching network between Antenna and Rectifier of RFID please tell me how reflections, if not matched, been modelled in Cadence Virtuoso. So whether I have to use any specifice ports or libraries  for modelling ...
    Posted to RF Design (Forum) by Jithin on Wed, Feb 26 2014
  • Re: Problem in viewing grid during Layout
    Sir, Even after keeping the ratio of major to minor spacing to 10, I was not able to see the grid without zooming. But when I zoom to a particular level the grid began to visible and the minor and major spacing seems to be exact as given the respective tabs. So is it because of the deep sub micron technology using I was unable to ...
    Posted to Custom IC Design (Forum) by Jithin on Tue, Aug 20 2013
  • Problem in viewing grid during Layout
    Sir/Madam,  I have been using Cadence Virtuoso 6.1.3.1 and the process chosen is 65nm CMOS .  While trying to Layout a design it is found that the grid is not visible but if we zoom till only one transistor, the grids become visible. My querry is Is there any issue if grid is not visible while doing Layout? or if its a problem then how ...
    Posted to Custom IC Design (Forum) by Jithin on Mon, Aug 19 2013
  • Re: Plotting through calculator
    Thank you for your reply. Yes that seems to be same problem. Regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Mon, Jun 10 2013
  • Re: Plotting through calculator
    HI, Thank you for the faster reply once again. What I have been doing in my design is just sweeping the gate voltage of an nmos transistor(65 nm cmos process), while keeping the transistor in saturation. The problem I have faced while doing experiment is that I was not able to plot the output using calculator even the current through the ...
    Posted to Custom IC Design (Forum) by Jithin on Wed, Jun 5 2013
  • Plotting through calculator
    Hi, I have been plotting a Ids vs Vds curve of nmos in 65 nm process and been saving all the parameters using the script "save M0.m1 :all" but the problem I am facing is that when I try to plot the current of transistor throgh the calculator an error is coming saying "Illegal expression . Is it because I have selected the ...
    Posted to Custom IC Design (Forum) by Jithin on Thu, May 30 2013
  • Re: compatibility of Assura 3.1 for 65 nm process
    Thank you for your kind reply. Regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Wed, May 29 2013
Page 1 of 3 (28 items) 1 | 2 | 3 | Next >