CDR for USB 3.0 PHY
Sir, I am modeling a
Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies
a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying
to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with
mean=0 and sd=4.03p and similarly deterministic jitter using ...