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  • power estimation using rc
    Hi all, I got a question about power estimation using cadence rc. I have two designs in HDL. Both of then have a 1-bit full adder. After synthsis, and post-simulation with the netlist with the same test data, I found the output toggle rate of these two 1-bit full adder are different, even though they have exactly the same input ...
    Posted to Logic Design (Forum) by RCsyn on Wed, Feb 29 2012
Page 1 of 1 (1 items)