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Page 1 of 1 (3 items)
  • Re: RE: NC-verilog logical bug
    Thanks a lot StephenH. You answered in great detail. so I just add a default option to the case statement  then my nc-verilog simulation and logic synthsis are matched right? always@*   case(sel)     2'h0  : do0 = di0;     2'h1  : do0 = di1;     2'h2  : ...
    Posted to Functional Verification (Forum) by Aiya on Thu, Feb 23 2012
  • Re: RE: NC-verilog logical bug
    Thank you Shalom, but could you explain in more detail ?  Logically, the output of mux should 1'b0 right? But using case or index coding style for mux implementation is more readable and explicit Is the do2 is the only option if I want to get correct logic output ? Or any syntax can be added to solve this ?
    Posted to Functional Verification (Forum) by Aiya on Thu, Feb 23 2012
  • NC-verilog logical bug
     I found a logical bug of simulation RTL code using NC-verilog. Here is the test RTL code of mux implementation, the input data of mux options are all zeroes (1'b0)  the select signal is unknown (2'bxx) The output result of do0 = 1'bx, do1 = 1'bx,  do2 = 1'b0, varies depending on the coding style, ...
    Posted to Functional Verification (Forum) by Aiya on Wed, Feb 22 2012
Page 1 of 1 (3 items)