Re: Looking for help with System Verilog in AMS
I don't put the -v in, ADE appears to do that when I hit the netlist and run button.
The file is added via the "Library Files" line in the ADE-L -> Simulation -> Options -> AMS Simulator
The bias_verilog.sv file is just one that gives me the error, too. Others listed in the -f also give the same problem (vga, dac, ...