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 Community Search 

Page 1 of 1 (7 items)
  • Re: SOC Encounter :: LEF File load Failed
     There are no site rows in your design (and also, what are the blocks you say are missing? standard cells? power rings?)   I still find your tech lef strange. If for example the unit defined is the micron, we see that you have a routing grid with a distance between the routing tracks (defined by the PITCH statement) of 10 microns, even ...
    Posted to Digital Implementation (Forum) by DavidMZ on Wed, Feb 15 2012
  • Re: remove inverter pairs from design?
    Prior to placement you can perform optimizations of your netlist using setOptMode. The -reclaimArea option for exemple is described like this: -reclaimArea {true | false} Controls whether timing optimization creates additional space by downsizing gates or deleting buffers, while maintaining worst slack and total negative slack. Default: false
    Posted to Digital Implementation (Forum) by DavidMZ on Wed, Feb 15 2012
  • Re: SOC Encounter :: LEF File load Failed
     Apparently it is still a tech lef problem, because, for example: "#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000" shows that either your tech lef file is badly defined, or that encounter is using a default value.  As stated by Kari previously, this type of ...
    Posted to Digital Implementation (Forum) by DavidMZ on Tue, Feb 14 2012
  • Re: ILM in encounter 8.1
    A recent tentative of modifying the .def files inside the ILM directory didn't change a thing to my problem (I replaced all the "PLACED" statements by "FIXED" ones, since I figured out I had many "PLACED" instances in the .def, even though everything is clearly "fixed" in my original design...) Also, my ...
    Posted to Digital Implementation (Forum) by DavidMZ on Fri, Feb 10 2012
  • Re: SOC Encounter :: Layout Routing Issues
    To sum up my answer in the other topic, it is normal behavior for trial route, which is sometimes launched after placing the design. Use nanoroute to fix this situation. About the metal used, you can set them for both trial route and nanoroute. For nanoroute you have 2 parameters in the form which are "bottomlayer" and "top ...
    Posted to Digital Implementation (Forum) by DavidMZ on Thu, Feb 9 2012
  • Re: SOC Encounter :: LEF File load Failed
    Right after placing the design, it is possible that a trial route is also launched. If true, then it is quite normal to have obvious violations such as overlapping wires. Run a nanoroute on your design, this should give you a more correct routing (not always DRC free though, but your small design can't possibly have such problems, unless you ...
    Posted to Digital Implementation (Forum) by DavidMZ on Thu, Feb 9 2012
  • ILM in encounter 8.1
    Hi there, as said in the title I'm trying to use ILM (Interface Logic Model) in encounter 8.1. In that aim I made a simple design consisting of one single instance of a block, which block is using ILM. My problem is, when I try to "placeDesign" as stated in the example top-level implementation flow using ILMs chapter of the ...
    Posted to Digital Implementation (Forum) by DavidMZ on Wed, Feb 8 2012
Page 1 of 1 (7 items)