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 Community Search 

Page 1 of 1 (3 items)
  • regarding leakage power in lvt cells
    hello everybody,                        can any body please explain why leakage power is more in lvt cells.what is relation between Vt and leakage.inversion can be acheived early if my Vt is less.how it vl effect leakage. i am searching for this answer for long time .can any body please ...
    Posted to Digital Implementation (Forum) by sathyarao on Sat, Sep 22 2012
  • Re: Regarding clock spec file
    hi,     in cts to reduce latency we are adding buffers(parallel) i.e we have to add high drive strength buffers near clock root and we have to come in descending order of buffer drive strength from clock root to clock sink i.e x12 near root x4 near sink...this is because to reduce DELAY VARIATION between the buffers.....and to maintain ...
    Posted to Digital Implementation (Forum) by sathyarao on Wed, Jul 18 2012
  • basic queries
    hi every one,                  plz answer to these questions   1.how to know the data path and clock path from timing reports( for setup and hold)  2. can i group macros if so can i group them according to clock  
    Posted to Digital Implementation (Forum) by sathyarao on Wed, Apr 18 2012
Page 1 of 1 (3 items)