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Page 1 of 1 (3 items)
  • Re: Edit Pin Name and Width
    Thanks for the prompt reply Andrew.  I might have not been very clear. The aim is to generate a schematic and a symbol programitically, instantiating several modules under a new schematic and a symbol which are connected to the above hierarchy level. The instantiation might have different bus widths, so the pins have to change accordingly. ...
    Posted to Custom IC SKILL (Forum) by cgurleyuk on Tue, Oct 8 2013
  • Edit Pin Name and Width
    Hello, I want to create a new schematic from the library which is created by me. I put an instance from this library to the new schematic. I want to change pin names of this instance. The problem is that some pin names have a bus notation ( Ex: A<3:0>) and i want to change width of this pin (Ex: A<5:0>). Cadence document says width of ...
    Posted to Custom IC SKILL (Forum) by cgurleyuk on Mon, Oct 7 2013
  • Re: set up parametric simulation to utilize multiple cores
    Hello Whlinfei, If you have access to ADE XL, you can define a parametric simulation by importing an already existing ADE L state or creating a test with a design variable, which you can parameterize by adding a variable specification in the ADE XL "Data View". In the run summary, you can verify the number of sweep points by inspecting ...
    Posted to Custom IC Design (Forum) by cgurleyuk on Sat, Aug 31 2013
Page 1 of 1 (3 items)