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 Community Search 

Page 1 of 2 (19 items) 1 | 2 | Next >
  • Re: define arrayed contacts in techfile
    Hi Derek, I remember experimenting with this constraint earlier, it has a limitation on number of adjacent via cuts, there's no point setting numcuts above 8 since every center via can be surrounded with max 8 vias so spacing is increased already at 3x3 via matrix which I don't want. Thanks, S.   
    Posted to Custom IC SKILL (Forum) by sPoK on Thu, May 30 2013
  • Re: define arrayed contacts in techfile
    Hi Andrew, I was wandering the same thing but I couldn't find a proper constraint. minLargeViaArraySpacing is the closest I could find but I'm not using arrays and anyway this constraint is only valid for VSR. What I need is inceased via (cut) spacing from 0.3 to 0.35 for via matrix 6x6 and above to satisfy density rules. It would be ...
    Posted to Custom IC SKILL (Forum) by sPoK on Wed, May 29 2013
  • Re: Geometric wire options (VLE)
    Meanwhile, I've found how to set min. number of cuts for geometric wire w/o XL and w/o using ITDB. Just add these lines to your local .cdsinit: envSetVal("layout" "viaWECutSpecified" 'boolean t) envSetVal("layout" "viaWECutRows" 'int 2) envSetVal("layout" "viaWECutColumns" ...
    Posted to Custom IC Design (Forum) by sPoK on Wed, Jan 23 2013
  • Re: Geometric wire options (VLE)
    Thanks Andrew, It's important when there is no VLS XL license, so only VLS L license is available. I understood your first suggestion as : 1. Dump extisting tech to .tf file 2. Edit needed sections 3. Load edited .tf file (-> merge or replace, I assume both options are executed in the virtual mem so PDK stays intact? )  
    Posted to Custom IC Design (Forum) by sPoK on Mon, Dec 17 2012
  • Geometric wire options (VLE)
    How can I set min. num. of cuts, wire width per metal, use of square collinear vias and other options for geometric wire without starting VXL, making my own contraint and setting it for default. I assume that the geometric wire has the same properties (or most of them) as the "real" wire.  Is this a bug or a feature? Since in ...
    Posted to Custom IC Design (Forum) by sPoK on Thu, Dec 13 2012
  • Re: "freeing" nets in 6.1.x VXL
    Hi Alex, I've tried everything you suggested but none worked out. It would be easy to fix this with "Select-> All shapes on net" and then change the connectivity, but this is not working also, no single shape selected. (there is a limit set for this function, 20k shapes, and I have around 10k). Or some skill code to convert ...
    Posted to Custom IC Design (Forum) by sPoK on Wed, Sep 5 2012
  • Re: "freeing" nets in 6.1.x VXL
    Hi Alex, css()~>route~>prop~>?? gives me only one nil, this is a correct command, right? (via is selected) Thanks, Srdjan
    Posted to Custom IC Design (Forum) by sPoK on Wed, Sep 5 2012
  • Re: "freeing" nets in 6.1.x VXL
    This is still a problem even in 6.1.5.500.10, nothing helps, niether extract neither update comp&nets. Placing pin will not help also (pic). There is no lxStickyNet set.  Why this can't be simple, if there is a pin placed anywhere in metal structure, all shapes/paths merged/added shoud get the same connectivity as pin. Even thru ...
    Posted to Custom IC Design (Forum) by sPoK on Mon, Sep 3 2012
  • Re: VCAR - Routing Specified Nets
    Finally I got it!Bussed net name in nets.txt file must be in the following format:bus_net[0]bus_net[1]..bus_net[31] instead of:bus_net<0>bus_net<1>..bus_net<31> and every bit of a bus must be stated. Thanks for the hint Andrew. BR
    Posted to Custom IC Design (Forum) by sPoK on Mon, Apr 2 2012
  • Re: VCAR - Routing Specified Nets
    I just found out that bused nets are not recognized at all, I tried with a nets.txt containing only one 16bit bus net, none loaded, tried with another 8bit bus net, but again the same error. No idea why is that happening :(  BR     
    Posted to Custom IC Design (Forum) by sPoK on Mon, Apr 2 2012
Page 1 of 2 (19 items) 1 | 2 | Next >