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 Community Search 

Page 1 of 3 (26 items) 1 | 2 | 3 | Next >
  • Re: net connectivity at the top level using TCL
    Thanks for the resposne. is there any way to do that from a tcl script? I'd like to automatically derive the connectivity of my net. Regards,  
    Posted to Functional Verification (Forum) by freitas on Thu, Jul 24 2014
  • OSS netlisting inherited gnd problem
    Dear all, we are having a strange issue when netlising our design with the OSS netlister (via runams command-line). Some of the inherited grounds nets are being strangely netliested. For instance, an inherited net that should be netlisted as \vss! ; is being netlisted as \vss_vss! ;  that is, its name is being duplicated. ...
    Posted to Custom IC Design (Forum) by freitas on Thu, Jul 24 2014
  • net connectivity at the top level using TCL
    Hello, I would like to use ncsim's (or simvision's) shell to find out the connectivity of a net. For example, if I have a wire named clk in my top-level, I would like to get a list of ports that this wire is connected to. Is this possible? Can you point me how to do that? Thanks, 
    Posted to Functional Verification (Forum) by freitas on Wed, May 28 2014
  • Re: reinvoking from the tcl shell
    It works as a charm! Thanks a lot!
    Posted to Functional Verification (Forum) by freitas on Mon, Oct 14 2013
  • reinvoking from the tcl shell
    Hello, I'd like to reinvoke the simulation using a tcl script. Is this possible? What's the tcl command to re-invoke the simulation? Actually, I would like a script that runs a preamble command to update the simulation options contained in the irun.f file before re-starting the simulation. That would allow me to re-start the simulation ...
    Posted to Functional Verification (Forum) by freitas on Sun, Sep 22 2013
  • controlling the analog solver within verilog
    Hello, I read in some application note that, starting from 12.x, incisiv would support Verilog system tasks (i.e., $cds_analog_on and $cds_analog_off) to control when the analog solver starts/stops. These tasks would simplify our verification environment.  Does anyone know if they are being supported? I can't find any ...
    Posted to Mixed-Signal Design (Forum) by freitas on Sat, Jul 20 2013
  • Non-piecewise constant argument is detected in the transition filter.
    Hello there, I have the following warning which I do not understand: Warning from spectre at time = 536.062 us during transient analysis `tran'.    WARNING (AHDLLINT-8004): "tb_disciplines.vams" 537: hvbms_tb.dut.vana_pad__R2E_supply__wreal_supply._cds_internal_R2E_supply_: Non-piecewise constant argument is ...
    Posted to Mixed-Signal Design (Forum) by freitas on Wed, Jun 26 2013
  • Re: bidirectional wreal modeling (resistor in wreal)
    I appologize. I guess we should start a AMS Verification forum, everytime I want to post something I am not sure were to place it. As for the resistor, all I needed was a wreal bidir net. Problem solved! I do have a continuous time view of that cell which is a conservative resistor model but sometimes I want to ...
    Posted to Mixed-Signal Design (Forum) by freitas on Mon, Mar 4 2013
  • bidirectional wreal modeling (resistor in wreal)
    Hello,I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.module res (p,n);inout p,n; //need a model here, something like tran t1(p,n)endmodule I've tried to check the inouts for the `wrealZState to determine what port is actually ...
    Posted to Mixed-Signal Design (Forum) by freitas on Sat, Mar 2 2013
  • bidirectional wreal modeling
     Hello,I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.module res (p,n);inout p,n; //need a model here, something like tran t1(p,n)endmodule I've tried to check the inouts for the `wrealZState to determine what port is ...
    Posted to Mixed-Signal Design (Forum) by freitas on Fri, Mar 1 2013
Page 1 of 3 (26 items) 1 | 2 | 3 | Next >