Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (5 items)
  • Re: rcp vs ple
     In a nutshell, PLE synthesis extracts information from your design/libraries and tries with some statistical methods to find out the expected capacitance and slew for your nets. Based on that information RTL Compiler tries to synthesize as best as possible to help you meet your timing.   RCP is a different story. RCP uses the ...
    Posted to Digital Implementation (Forum) by Fotios Nt on Fri, Jun 6 2014
  • Re: RTL Compiler: VCD Annotation and CPF
     Hi steven,   This is somewhat strange, could you please file a case in support.cadence.com ?    Regards, Fotis
    Posted to Logic Design (Forum) by Fotios Nt on Fri, Apr 26 2013
  • Re: Unable to map design without a suitable latch. [MAP-3] [synthesize]
     Hello Li,   Your library doesnt seem to contain a latch. Please open it and ensure that you have latch cells, and they aren't marked unusable   If you do not want to use latches, please take a look in the HDL Modeling in Encounter® RTL Compiler manual, where it is explained that , depending on the way you code verilog, ...
    Posted to High Level Synthesis (Forum) by Fotios Nt on Thu, Apr 25 2013
  • Re: RTL Compiler: VCD Annotation and CPF
     Hi Steven,   The solution to your problem would be one of the following.   Solution #1: Annotate switching activities for each power mode in your cpf file. Check update_power_mode -activity_file command .   Solution #2: Your flow should look something like this: read_cpf ...
    Posted to Logic Design (Forum) by Fotios Nt on Thu, Apr 25 2013
  • Re: Power Difference between Analog Simulation and RTL complier estimation
     RTL compiler has a default value for input switching activitiy (i.e how fast inputs change)  Directly from the rc-lp manual: If you want a fast power analysis you can choose to apply the default switching activities. The tool default signal probability is 0.5, the tool default toggle rate is 0.02, and the default toggle rate unit is ...
    Posted to Logic Design (Forum) by Fotios Nt on Tue, Apr 2 2013
Page 1 of 1 (5 items)