Re: Unable to map design without a suitable latch. [MAP-3] [synthesize]
Your library doesnt seem to contain a latch. Please open it and ensure that you have latch cells, and they aren't marked unusable
If you do not want to use latches, please take a look in the HDL Modeling in Encounter® RTL Compiler manual, where it is explained that , depending on the way you code verilog, ...