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 Community Search 

Page 1 of 1 (5 items)
  • RTL Compiler
     Hi all, I am new to Cadence synthesis Tool. Would like to get into the RTL compiler in future. Where do I get help documents about Synthesis Design Constraints commands? Thanks, Sam  
    Posted to Logic Design (Forum) by Mandate on Wed, Dec 7 2011
  • Re: RE: Gate level Simulation
     Hi Tim, With testbench I tried simulatiing the synthesiszed netlist without SDF file. It gave approximately 0.7ns clock to q delay. I think, it is taking only the gate delay from the standard cell library and It doesn't have the net or path delay. Would like to know whether my understanding is correct? Is SDF file output of ...
    Posted to Functional Verification (Forum) by Mandate on Tue, Oct 4 2011
  • Re: RE: Gate level Simulation
     Hi Tim, With testbench I tried simulatiing the synthesiszed netlist without SDF file. It gave approximately 0.7ns clock to q delay. I think, it is taking only the gate delay from the standard cell library and It doesn't have the net or path delay. Would like to know whether my understanding is correct? Is SDF file output of synthesis ...
    Posted to Functional Verification (Forum) by Mandate on Tue, Oct 4 2011
  • Gate level Simulation
    Hi All, I am using Candence IES tool, and also new to cadence tools. What are the inputs required for GATE level simulation (after synthesis)? I have standard library file in .v format and .v netlist. Is this enough for gate level simulation? Please help me in this Thanks, Sam
    Posted to Functional Verification (Forum) by Mandate on Mon, Oct 3 2011
  • Gate Level Simulation
     Hi All, I am using Candence IES tool, and also new to cadence tools. What are the inputs required for GATE level simulation (after synthesis)? I have standard library file in .v format and .v netlist. Is this enough for gate level simulation? Please help me in this Thanks, Sam      
    Posted to Functional Verification (Forum) by Mandate on Mon, Oct 3 2011
Page 1 of 1 (5 items)