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 Community Search 

Page 1 of 19 (183 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Sweeping component parameters for many components in ADE GXL
    Let's say I have 20 transistors in a circuit and all of them have same value of W. If I want to DC sweep that W as a component parameter, the tool only allows you to select one component. But I need to sweep W which is common to ALL transistors in a circuit. How can I achieve that? The most obvious solution was to declare a Variable and ...
    Posted to Custom IC Design (Forum) by Kabal on Sun, Jun 15 2014
  • Re: AMS Simulation fails with error 127?
    Oh well... I had to run runSimulation file from netlist directory directly in order to figure out that it didn't run because I did not have a library called libreadline.so.5  "CAD on Linux in 2014"...
    Posted to Mixed-Signal Design (Forum) by Kabal on Sat, May 31 2014
  • AMS Simulation fails with error 127?
    I have set up the basic mixed-signal testbench. Just imported a verilog file with clock generator, created a symbol for it and added it in a simple testbench where it is driving schematics built inverter cell.  I arranged the ADE GXL simulator with ams option. I Set up the connect modules for 1.8V. Everything seems fine. When I run the ...
    Posted to Mixed-Signal Design (Forum) by Kabal on Sat, May 31 2014
  • License problems running AMS simulation in ADE GXL
    I set up some testbench for AMS simulation. Configured the ADE GXL, selected "ams" as a Simulator. When running it fails, the log file at the end says: " FATAL (SPECTRE-208) : No license available to run Virtuoso (R) Spectre. " I don't get it why does it complain? We can run for example regular analog circuit simulations ...
    Posted to Mixed-Signal Design (Forum) by Kabal on Thu, May 1 2014
  • Re: Connecting Global power to Pins of instances
    Those were basically tieLO/HI pins. I just had to run explicit command for their connection. solved.
    Posted to Digital Implementation (Forum) by Kabal on Tue, Mar 4 2014
  • Connecting Global power to Pins of instances
    Sometimes I noticed when you do operation of connecting global power to pins of instances and then do Check operation it says that power is not connected to some instances.  I am curious is it something normal? Does it mean that specific instances are kind of optimized? Or should I be worried about it? All my instances have VDD! and GND! ...
    Posted to Digital Implementation (Forum) by Kabal on Fri, Feb 28 2014
  • Re: LVS Operation suddenly broke
    Alright, it broke because the subcircuit.cdl file which had description of those cells was not included during netlist export operation (it just suddenly disappeared from the menu). The thing is, this line with path to that file was forever in that menu, and I just didn't notice its absence at the beginning.   Now it works. 
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • Re: LVS Operation suddenly broke
    Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS. By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its ...
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • Re: LVS Operation suddenly broke
    Thanks for reply, 1) Yes, I am using Assura LVS. 2) I am not doing blackbox LVS, I just have custom schematics with transistors and other different elements, then I export the netlist, then I pass it through the LVS script as always and export to final netlist for LVS in CDL format. Always been doing it and it worked, but now it does not. The ...
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • LVS Operation suddenly broke
    I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors: *ERROR* cell 'ind' is not defined. *ERROR* cell 'pcdcap' is not ...
    Posted to Custom IC Design (Forum) by Kabal on Mon, Feb 24 2014
Page 1 of 19 (183 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »