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Page 1 of 18 (179 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: Connecting Global power to Pins of instances
    Those were basically tieLO/HI pins. I just had to run explicit command for their connection. solved.
    Posted to Digital Implementation (Forum) by Kabal on Tue, Mar 4 2014
  • Connecting Global power to Pins of instances
    Sometimes I noticed when you do operation of connecting global power to pins of instances and then do Check operation it says that power is not connected to some instances.  I am curious is it something normal? Does it mean that specific instances are kind of optimized? Or should I be worried about it? All my instances have VDD! and GND! ...
    Posted to Digital Implementation (Forum) by Kabal on Fri, Feb 28 2014
  • Re: LVS Operation suddenly broke
    Alright, it broke because the subcircuit.cdl file which had description of those cells was not included during netlist export operation (it just suddenly disappeared from the menu). The thing is, this line with path to that file was forever in that menu, and I just didn't notice its absence at the beginning.   Now it works. 
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • Re: LVS Operation suddenly broke
    Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS. By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its ...
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • Re: LVS Operation suddenly broke
    Thanks for reply, 1) Yes, I am using Assura LVS. 2) I am not doing blackbox LVS, I just have custom schematics with transistors and other different elements, then I export the netlist, then I pass it through the LVS script as always and export to final netlist for LVS in CDL format. Always been doing it and it worked, but now it does not. The ...
    Posted to Custom IC Design (Forum) by Kabal on Tue, Feb 25 2014
  • LVS Operation suddenly broke
    I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors: *ERROR* cell 'ind' is not defined. *ERROR* cell 'pcdcap' is not ...
    Posted to Custom IC Design (Forum) by Kabal on Mon, Feb 24 2014
  • Question regarding a SITE definition
    Are SITE DEFINITIONS something what designer must re-write for every cell? Or it is something what I am supposed to receive from the foundry with the LEF file? How does it usually work out?   thanks. 
    Posted to Digital Implementation (Forum) by Kabal on Thu, Feb 20 2014
  • Re: Wrong angle for pads when placing footprint
    Basically I am using only my own padstacks, and had them saved in some folder. I just created PADPATH env. variable, added that path there. Then went back to design and selected to refresh padstacks. Now it shows up correctly.  Thanks. 
    Posted to PCB Design (Forum) by Kabal on Wed, Feb 19 2014
  • Wrong angle for pads when placing footprint
     Allegro PCB  I created some rectangular pad. Then created a footprint and used that pad I created before with 90deg angle. However, once I instantiated that footprint in PCB Layout for some reason the footprint has all its pads back to 0deg.  Why is that happening?
    Posted to PCB Design (Forum) by Kabal on Tue, Feb 18 2014
  • Multiple MinArea, No-Grid and Spacing Errors
    Using Encounter 13.2 Defined .capTbl, .tch, .lef files, defined timing and other settings in viewdefinition. Got the design placed and routed. Once I start checking the design with verifyGeometry I see hundreds of thousands errors of different type like: Antenna MinArea No-Grid OffGrid Spacing Short Using the following commands did not ...
    Posted to Digital Implementation (Forum) by Kabal on Sun, Feb 16 2014
Page 1 of 18 (179 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »